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AD5259 Datasheet(PDF) 9 Page - Analog Devices

Part No. AD5259
Description  Nonvolatile, I2C-Compatible 256-Position, Digital Potentiometer
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD5259
Preliminary Technical Data
Rev. PrJ 7/22/04 | Page 9 of 14
I2C COMPATIBLE 2-WIRE SERIAL BUS
1.
The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 4). The
following byte is the Slave Address Byte, which consists of
the slave address followed by an R/W bit (this bit
determines whether data is read from or written to the
slave device).
The AD5259 has two tri-state configurable address bits,
AD0 and AD1 (see Table 4). The slave whose address
corresponds to the transmitted address responds by pulling
the SDA line low during the ninth clock pulse (this is
termed the acknowledge bit). At this stage, all other devices
on the bus remain idle while the selected device waits for
data to be written to or read from its serial register. If the
R/W bit is high, the master reads from the slave device. If
the R/W bit is low, the master writes to the slave device.
2.
Writing:
In the write mode, the last bit(R/W) of the
Address Byte is logic low. The second byte is the
Instruction Byte. The first 3 bits of the Instruction Byte are
the command bits(see Table 5). The final 5 bits indicate
which EEMEM location the pointer moves to. The user
must choose whether to write to the RDAC register,
EEMEM register, or activate the software write protect(see
Tables 6-8).
The final byte is the Data Byte MSB first. In the case of the
write protect mode, data is not being stored. Rather, a
logic high in the LSB will enable write protect and a logic
low will disable write protect.
3.
Storing/Restoring:
In this mode, only two bytes are
necessary; Address and Instruction Bytes. The last bit
(R/W) of the Address Byte is logic low. The first 3 bits of
the Instruction Byte are the command bits(see Table 5).
The two choices are transfer data from RDAC to
EEMEM(Store) or from EEMEM to RDAC(Restore). The
final 5 bits are all zeros(see Tables 9-10).
4.
Reading:
Assuming the register of interest was not just
written to, it is necessary to write a dummy Address and
Instruction Byte. The Instruction Byte will vary depending
on whether the data that is wanted is the RDAC register,
EEMEM register, or Tolerance register(see Tables 11-13).
The Tolerance register can be read back
consecutively(Table 13i) or individually(Table13ii). Refer
to page 8 for detailed information on the interpretation of
the tolerance bytes. After the dummy Address and
Instruction Bytes are sent, a repeat start is necessary. After
the repeat start, another Address Byte is needed except this
time, the R/W bit is logic high. Following this Address
Byte is the Read Back Byte containing the information
requested in the Instruction Byte.
5.
After all data bits have been read or written, a STOP
condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line
high during the 10th clock pulse to establish a STOP
condition (see Figure 6). In read mode, the master issues a
No Acknowledge for the ninth clock pulse (i.e., the SDA
line remains high). The master then brings the SDA line
low before the 10th clock pulse, and then raises SDA high to
establish a STOP condition (see Figure 7).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and
instructing the part only once. For example, after the RDAC has
acknowledged its Slave Address and Instruction Bytes in the
write mode, the RDAC output is updated on each successive
byte. If different instructions are needed, the write/read mode
has to start again with a new Slave Address, Instruction, and
Data Byte. Similarly, a repeated read function of the RDAC is
also allowed.




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