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MF0128M-04AAXX Datasheet(PDF) 4 Page - Mitsubishi Electric Semiconductor |
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MF0128M-04AAXX Datasheet(HTML) 4 Page - Mitsubishi Electric Semiconductor |
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4 / 32 page  MITSUBISHI STORAGE CARD Preliminary CompactFlash CARDS MITSUBISHI ELECTRIC 4 Oct.1999. Rev. 0.2 Signal Description(Continued) Signal Name I/O Pin No. Description Attribute Memory Select[REG#] (PC Card Memory Mode) I 44 When this signal is asserted, access is limited to Attribute Memory with OE#/WE# and I/O Space Attribute Memory Select[REG#] (PC Card I/O Mode) with IORD#/IOWR#. Attribute Memory Select[REG#] (True IDE Interface) This input signal is not used for this mode and should be connected to Vcc by the host. Battery Voltage Detect[BVD2] (PC Card Memory Mode) O 45 This output is driven to a high-level. Audio Digital Waveform[SPKR#] (PC Card I/O Mode) SPKR# is kept negated because this Card does not have digital audio output. DASP# (True IDE Interface) I/O This signal is the DISK Active/Slave Present signal in the Master/Slave handshake protocol. Card Reset[RESET] (PC Card Memory Mode) I 41 By assertion of this signal, all registers of this Card are cleared. This signal should be kept to High-Z by Card Reset[RESET] (PC Card I/O Mode) the host for at least 1ms after Vcc applied. Card Reset[RESET#] (True IDE Interface) This input pin is the active low hardware reset from the host. Wait[WAIT#] (PC card Memory Mode) O 42 This signal is asserted to delay completion of the memory or I/O access cycle. Wait[WAIT#] (PC card I/O Mode) IORDY (True IDE Interface) Input Port Acknowledge[INPACK#] (PC Card I/O Mode) O 43 This signal is asserted when the Card is selected and can respond to an I/O Read cycle at the address on the address bus. Input Port Acknowledge[INPACK#] (True IDE Interface) This signal is not used for this mode and should not be connected at the host. Battery Voltage Detect[BVD1] (PC Card Memory Mode) O 46 This output is driven to a high-level. STSCHG# (PC Card I/O Mode) This signal is asserted low to alert the host to changes in the status of Configuration Status Register in the Attribute Memory Space. PDIAG# (True IDE Interface) I/O This signal is the Pass Diagnostic signal in the Master/Slave handshake protocol. Voltage Sense[VS1, VS2] O 33, 40 VS1 is grounded so that the Card CIS can be read at 3.3V and VS2 is N.C. Cable Select[CSEL] (PC Card Memory Mode) - 39 This signal is not used for this mode. Cable Select[CSEL] (PC Card I/O Mode) - Cable Select[CSEL] (True IDE Interface) I This signal is used to configure this Card as a Master or a Slave. When this signal is grounded, this Card is configured as a Master. When this signal is Open, this Card is configured as a Slave. Vcc - 13, 38 5V or 3.3V power. GND - 1, 50 Ground. |
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