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AN-6003 Datasheet(PDF) 3 Page - Fairchild Semiconductor

Part # AN-6003
Description  Shoot-through in Synchronous Buck Converters
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

AN-6003 Datasheet(HTML) 3 Page - Fairchild Semiconductor

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Shoot-through in Synchronous Buck Regulators
AN-6003
04/25/2003
3
When the adaptive gate circuit switches, the internal
MOSFET gate voltage will be:
()
V
1
.
4
5
2
.
1
2
2
V
1
=
+
+
In this example, if there were no delay in the circuit,
the HDRV would turn on when the low-side
MOSFET has just begun to discharge, causing a very
high shoot-through current.
Much of the problem in the above circuit is the
damping resistor. If a damping resistance is
necessary, place a Schottky diode across the resistor
(as shown below) to reduce the effect the damping
resistor will have on the adaptive gate drive.
R
DRIVER
R
Damping
H.S. MOSFET
1V
HDRV
LDRV
Delay
H.S. MOSFET
R
GATE
C
GS
C
GD
D
S
G
Q2
Figure 6. Schottky diode reduces damping
resistor error in adaptive gate drive
When using the schottky, the internal gate node will
be at:
()
GATE
DRIVER
DRIVER
)
I
(
GS
R
R
R
V
1
5
.
0
V
+
+
=
or 2.1V for our example. A dramatic improvement.
Furthermore, the Schottky reduces the duration of the
shoot-through step, since only R
GATE + RDRIVER will be
discharging C
GS, rather than the sum of
R
GATE + RDAMPING + RDRIVER .
Table 1 below illustrates the performance
improvement in our example with and without the
Schottky diode:
No
Schottky
With
Schottky
Comparator Flips @ VGS(INT) =
4.1
2.1
V
VGS(INT) after 20nS delay
2.23
1.14
V
VSTEP Peak
2.50
1.25
V
Peak current
36
0.29
A
Power Loss @ FSW=300KHz
1100
20
mW
Conditions: Typical low-side MOSFET, 25nS
delay from comparator sense to beginning of SW
node rise, 19V
IN, 10nS SW node rise time.
Table 1 . Peak Currents with and without
Schottky with R
DAMPING = 5Ω .
MOSFET Choices
MOSFET characteristics can have a dramatic effect
on how much shoot-through current can be induced
by the gate step. The worst case for shoot-through is
an infinitely fast (0 rise time) on the drain node. The
amount of gate step is largely determined by the
ration of C
GS and CGD .
Once the size of the gate step
is determined (eq. 1 above), the peak magnitude of
the shoot-through current can be calculated as :
(
)
)
MIN
(
TH
STEP(MAX)
M
)
MAX
(
PEAK
V
V
G
K
I
(2)
where G
M is the transconductance (in S, or A/V)
given in the datasheet. While only a small
percentage of MOSFETs exhibit V
TH(MIN) at room
temperature, V
TH goes down with increasing junction
temperature, therefore V
TH(MIN) is a good proxy for the
V
TH at the operating junction temperature of the
MOSFET. Subsequent calculations use V
TH(MIN) for
this reason.
G
M is not really a contstant, however, and its value is
greatly reduced low enhancement voltages (V
GS-VTH).
In these calculations we use a factor "K" from the
graph below, which is typical of G
M with low values
of enhancement. The X axis of Figure 7 is calculated
as
)
MIN
(
TH
)
MIN
(
TH
GS
V
V
V
0.0
0.2
0.4
0.6
0.8
1.0
0%
50%
100%
150%
200%
250%
300%
Normalized Enhancement Voltage
Figure 7 GM factor (K)
Table 2 shows the relevant MOSFET characteristics
which determine the maximum shoot-through
current.
MOSFET
CGS
CGD
Typical
VTH
Min
VTH
GM
MOSFET1
3,514
307
1.6
1
86
MOSFET2
5,070
230
1.2
0.8
97
MOSFET3
4,942
315
1.6
1
80
MOSFET4
3,888
401
1.6
1
135
MOSFET5
6,324
281
1.15
0.6
90
Table 2 . Low-Side MOSFET Characteristics


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