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RECEIVER SWITCHING CHARACTERISTICS

SN65MLVD2

SN65MLVD3

SLLS767 – NOVEMBER 2006

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MAX

UNIT

Propagation delay time, low-to-high-level output

2

6

ns

Propagation delay time, high-to-low-level output

2

6

ns

Output signal rise time

1

2.3

Output signal fall time

1

2.3

ns

Type 1

90

210

ps

Type 2

45

250

Part-to-part skew

1

ns

125 MHz clock input

10

ps

8

ps

Type 1

500

ps

Type 2

450

ps

Type 1

8

ps

Type 2

8

ps

Enable time, high-impedance-to-high-level output

15

ns

Enable time, high-impedance-to-low-level output

15

ns

Disable time, high-level-to-high-impedance output

10

ns

Disable time, low-level-to-high-impedance output

10

ns

(1)

All typical values are at 25

°C and with a 3.3-V supply voltage.

(2)

Jitter measured by triggering off of the input source to track out the associated input jitter.

(3)

Stimulus jitter has been subtracted from the numbers.

(4)

Measured over 75K samples

(5)

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

A

6

I

M-LVDS Non-inverting input

B

7

I

M-LVDS Inverting input

R

3

O

Data output from receivers

RE

2

I

Receiver enable, active low, enables all receivers

GND

4, 5

Circuit ground

1, 8

Supply voltage

DEVICE FUNCTION TABLES

TYPE-1 RECEIVER (SN65MLVD2)

TYPE-2 RECEIVER (SN65MLVD3)

RE

R

RE

R

L

H

L

H

–35 mV

≤ V

L

?

65 mV

≤ V

L

?

L

L

L

L

X

H

Z

X

H

Z

X

Open

Z

X

Open

Z

Open Circuit

L

?

Open Circuit

L

L

(1)

H=high level, L=low level, Z=high impedance, X=Don’t care, ?=indeterminate

5

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