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ADUM1410 Datasheet(PDF) 8 Page - Analog Devices |
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ADUM1410 Datasheet(HTML) 8 Page - Analog Devices |
8 / 20 page ADuM1410/ADuM1411/ADuM1412 Rev. E | Page 8 of 20 Parameter Symbol Min Typ Max Unit Test Conditions 10 Mbps (BRW Grade Only) VDD1 Supply Current IDD1 (10) 5 V/3 V Operation 4.6 6.5 mA 5 MHz logic signal frequency 3 V/5 V Operation 2.6 3.8 mA 5 MHz logic signal frequency VDD2 Supply Current IDD2 (10) 5 V/3 V Operation 2.6 3.8 mA 5 MHz logic signal frequency 3 V/5 V Operation 4.6 6.5 mA 5 MHz logic signal frequency For All Models Input Currents IIA, IIB, IIC, IID, ICTRL1, ICTRL2, IDISABLE −10 +0.01 +10 μA 0 ≤ VIA,VIB, VIC,VID ≤ VDD1 or VDD2, 0 ≤ VCTRL1,VCTRL2 ≤ VDD1 or VDD2, VDISABLE ≤ VDD1 Logic High Input Threshold VIH 5 V/3 V Operation 2.0 V 3 V/5 V Operation 1.6 V Logic Low Input Threshold VIL 5 V/3 V Operation 0.8 V 3 V/5 V Operation 0.4 V VDD1, VDD2 − 0.1 VDD1, VDD2 V IOx = −20 μA, VIx = VIxH Logic High Output Voltages VOAH, VOBH, VOCH, VODH VDD1,VDD2 − 0.4 VDD1,VDD− 0.2 V IOx = −4 mA, VIx = VIxH 0.0 0.1 V IOx = 20 μA, VIx = VIxL 0.04 0.1 V IOx = 400 μA, VIx = VIxL Logic Low Output Voltages VOAL, VOBL, VOCL, VODL 0.2 0.4 V IOx = 4 mA, VIx = VIxL SWITCHING SPECIFICATIONS ADuM1411ARW and ADuM1412ARW Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 tPHL, tPLH 25 70 100 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels Propagation Delay Skew6 tPSK 50 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching7 tPSKCD/OD 50 ns CL = 15 pF, CMOS signal levels ADuM141xBRW Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 tPHL, tPLH 25 35 60 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|5 PWD 5 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 tPSK 30 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional Channels7 tPSKCD 5 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Opposing-Directional Channels7 tPSKOD 6 ns CL = 15 pF, CMOS signal levels For All Models Output Rise/Fall Time (10% to 90%) tR/tf CL = 15 pF, CMOS signal levels 5 V/3 V Operation 2.5 ns 3 V/5 V Operation 2.5 ns Common-Mode Transient Immunity at Logic High Output8 |CMH| 25 35 kV/μs VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V Common-Mode Transient Immunity at Logic Low Output8 |CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 5 V/3 V Operation 1.2 Mbps 3 V/5 V Operation 1.1 Mbps Input Enable Time9 tENABLE 2.0 μs VIA, VIB, VIC, VID = 0 or VDD1 |
Similar Part No. - ADUM1410 |
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Similar Description - ADUM1410 |
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