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PDM41024SA12TSOATY Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers |
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PDM41024SA12TSOATY Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers |
7 / 8 page PDM41024 Rev. 3.3 - 4/09/98 7 1 2 3 4 5 6 7 8 9 10 11 12 Write Cycle No. 3 (Chip Enable Controlled) AC Electrical Characteristics SHADED AREA = PRELIMINARY DATA Notes referenced are after Data Retention Table Description -10(7) -12(7) -15 WRITE Cycle Sym Min. Max. Min. Max. Min. Max. Units WRITE cycle time tWC 10 12 15 ns Chip enable active time tCW 10 10 11 ns Address valid to end of write tAW 10 10 11 ns Address setup time tAS 0 00 ns Address hold from end of write tAH 0 00 ns Write pulse width tWP1 8 811 ns Write pulse width tWP2 8 812 ns Data setup time tDS 7 77 ns Data hold time tDH 0 00 ns Write disable to output in low Z(1,3) tLZWE 0 00 ns Write enable to output in high Z(1,3) tHZWE 777 ns tWC tAW tWP1 tCW tAH tAS tDH tDS ADDR CE1 CE2 WE DOUT HIGH-Z DIN DATA VALID NOTE: Output Enable (OE) is inactive (high) |
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