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ADV7392BCPZ Datasheet(PDF) 10 Page - Analog Devices |
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ADV7392BCPZ Datasheet(HTML) 10 Page - Analog Devices |
10 / 96 page ADV7390/ADV7391/ADV7392/ADV7393 Rev. 0 | Page 10 of 96 IN MASTER/SLAVE MODE IN SLAVE MODE CLKIN CONTROL OUTPUTS t9 t10 Cr2 Cb2 Cr0 Cb0 Y0 Y1 Y2 Y3 t12 t14 t11 t13 HSYNC VSYNC CONTROL INPUTS PIXEL PORT PIXEL PORT Figure 4. SD Input, 16-Bit 4:4:4 RGB (Input Mode 000) CONTROL OUTPUTS t9 t10 t11 G0 G1 G2 B0 B1 B2 R0 R1 R2 t12 t14 t13 PIXEL PORT PIXEL PORT PIXEL PORT CLKIN HSYNC VSYNC CONTROL INPUTS Figure 5. ED/HD-SDR Input, 16-Bit 4:2:2 YCrCb (Input Mode 001) CLKIN* CONTROL OUTPUTS Cr2 Y2 Cb2 Y1 Cr0 Y0 Cb0 t9 t10 t12 t11 t12 t11 t14 t13 PIXEL PORT HSYNC VSYNC CONTROL INPUTS *LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2. Figure 6. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC), Input Mode 010 |
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