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S71WS512N80BAEZZ2 Datasheet(PDF) 8 Page - SPANSION |
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S71WS512N80BAEZZ2 Datasheet(HTML) 8 Page - SPANSION |
8 / 142 page 8 S71WS512NE0BFWZZ_00_A1 June 28, 2004 Advan ce In form ati o n Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (FBGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Pin Description A22–A0 = 23 Address Inputs (Common) A23 = 1 Address Inputs (Flash) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE#1pS = Chip Enable1 (pSRAM) CE#2pS = Chip Enable2 (pSRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RDY = Ready Output CLK = Clock Input AVD# = Address Valid Input UB# = Upper Byte Control (SRAM) LB# = Lower Byte Control (SRAM) RESET# = Hardware Reset Pin, Active Low (Flash) WP# = Hardware Write Protect (Flash) ACC = Acceleration pin (Flash) VCCf = Flash 1.8 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VCCps = pSRAM Power Supply VIOps = pSRAM Output buffer Power Supply Vss = Device Ground (Common) NC = Pin Not Connected Internally RFU = Reserved for Future Use |
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