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INDUSTRIAL TEMPERATURE RANGE

IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN

SIGNAL PROCESSING

High performance oversampling Analog-to-Digital Converters (ADC) and

Digital-to-Analog Converters (DAC) are used in the IDT821034 to provide

the required conversion accuracy. The associated decimation and inter-

polation filters are realized with both dedicated hardware and Digital Sig-

nal Processor (DSP). The DSP also handles all other necessary functions

such as PCM bandpass filtering and sample rate conversion.

Transmit Signal Processing

In the transmit path, the analog input signal is received with a gain

setting amplifier. The signal gain is set by the resistive feedback network

as shown in the application circuit (Figure 5). The output of the gain

setting amplifier is connected internally to the input of the anti-alias filter

for the oversampling ADC. The digital output of the oversampling ADC

is decimated and sent to the DSP. The transmit filter is implemented in

the DSP as a digital bandpass filter. The filtered signal is further decimated

and compressed to PCM format.

Transmit PCM Interface

The transmit PCM interface clocks the PCM data out of DX pin on rising

edges of BCLK according to the time slot assignment. The frame sync

(FS) pulse identifies the beginning of a transmit frame, or time slot zero.

The time slots for all channels are referenced to FS. The IDT821034

contains user programmable Transmit Time Slot Register for each transmit

channel. The register is 7 bits wide and can accommodate up to 128 time

slots (corresponding to the maximum BCLK frequency of 8.192 MHz) in

each frame. The PCM Data is transmitted serially on DX pin with the Most

Significant Bit (MSB), or Bit 7, first.

When the device is first powered up, all transmit time slots are disabled

with Transmit Time Slot Registers set to zero. DX pin remains in high-

impedance state. To power up or power down each transmit channel,

Configuration Register and the corresponding Time Slot Register must be

programmed.

Receive Signal Processing

In the receive path, the PCM code is received at the rate of 8,000

samples per second. The PCM code is expanded and sent to the DSP

for interpolation and receive channel filtering function. The receive filter

is implemented in the DSP as a digital lowpass filter. The filtered signal

is then sent to an oversampling DAC. The DAC output is post-filtered

and then delivered at VFRO pin by a power amplifier. The amplifier can

drive resistive load higher than 2 k

Ω.

Receive PCM Interface

The receive PCM interface clocks the PCM data into DR pin on falling

edges of BCLK according to the time slot assignment. The receive time

slot definition and programming is similar to that of the transmit time slot.

The IDT821034 contains a user programmable Receive Time Slot Register

for each receive channel. The register is 7 bits wide and can accommodate

up to 128 time slots (corresponding to the maximum BCLK frequency of

8.192 MHz) in each frame. The PCM Data is received serially on DR pin

with the MSB (Bit 7) first.

When the device is first powered up, all receive time slots are disabled

with Receive Time Slot Registers set to zero. Data on DR pin is ignored. To

power up or power down each receive channel, Configuration Register

and the corresponding Time Slot Register must be programmed.

Serial Control Interface

A Serial Control Interface is provided for a microprocessor to access

the control and status registers of IDT821034. The control registers include

Configuration Register, Time Slot Registers, SLIC Control Registers and

Gain Adjustment Registers. They are used to program the working modes

of CODEC and SLIC. The status registers include SLIC Status Registers.

They are used to monitor SLIC functions. All registers are 8 bits wide.

The Serial Control Interface consists of CO, CI, CS and CCLK pins

(see Figure 1). A microprocessor initiates a write or read cycle after low

level is asserted on CS pin. In the microprocessor write cycle, 8 bits of

serial data on CI pin are shifted into the device at falling edges of CCLK.

In the microprocessor read cycle, 8 bits of serial data are shifted out of

the device on CO pin at rising edges of CCLK. At the end of each 8-bit

transaction, the microprocessor sets CS high to terminate the cycle.

Multiple accesses to the device are separated by an idle state (high

level) of CS. The width of CS high level is at least three CCLK cycles.

The IDT821034 has a Configuration Register. Its register bits are

designated CR.7 - CR.0. The definition of the bits in Configuration Register

is shown in Table 1. If the leading data bit on CI pin is ‘1’ in a

microprocessor write cycle, the 8-bit data on CI pin is latched into

Configuration Register with MSB first.

There are eight Time Slot Registers for four transmit channels and

four receive channels. The definition of the bits in Time Slot Register is

shown in Table 2. Since PCM sample rate is 8k samples/sec and each

sample is 8 bits wide, each time slot occupies 64 kbits/sec of data rate.

The number of time slots in a frame is equal to the ratio of the bit

clock frequency (BCLK) to 64 kHz. For the maximum BCLK frequency

of 8.192 MHz, the number of time slots in a frame is 8.192MHz/64kHz,

or 128. The minimum number of time slots (corresponding to the

minimum BCLK frequency of 512 kHz) in a frame is 8. The relationship

between frequently used BCLK frequencies and the number of time slots

in a frame is shown in Table 3. Bit 6-0 in each Time Slot Register identify

the time slot number (0 to 127) of the corresponding transmit or receive

channel. Time Slot Registers can be accessed by specifying the transmit/

receive select (CR.1 and CR.0) and channel address (CR.3 and CR.2)

in Configuration Register. If CR.6 = ‘0’ and the leading data bit on CI pin

is ‘0’ in a microprocessor write cycle, the 8-bit data on CI pin is latched

into the selected Time Slot Register with MSB first.

There are four SLIC Control Registers for four channel SLIC signaling

control. The definition of the bits in a SLIC Control Register is shown in

Table 4. SLIC Control Registers can be accessed by specifying the

channel address (CR.3 and CR.2) in Configuration Register. If CR[6:4] =

‘101’ and the leading data bit on CI pin is ‘0’ in a microprocessor write or

read cycle, the 8-bit data on CI pin is latched into the selected SLIC

Control Register with MSB first.

There are four SLIC Status Registers for four channel SLIC monitoring.

The bits in each SLIC Status Register are mapped to the SLIC signaling

output and I/O pins of the corresponding channel as shown in Table 5. It

should be noted that the last 3 bits of the SLIC Status Register are always

mapped to I/O1_0, I/O2_0 and I/O3_0. This feature allows a rapid read

process of the SLIC status when Channel 0 is selected. The SLIC Status

Registers can be accessed by specifying the channel address (CR.3

and CR.2) in the Configuration Register. If CR[6:4] = ‘101’, as a result of

the previous write to the Configuration Register, the subsequent

microprocessor cycle is a read cycle. The content of the selected SLIC

Status Register is shifted out of the device on CO pin with MSB first.

There are 16 Gain Adjustment Registers for both transmit and

receive paths of four channels. For each path, there are two