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TPS40140RHHR Datasheet(PDF) 5 Page - Texas Instruments |
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TPS40140RHHR Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 65 page  www.ti.com TPS40140 DUAL OR 2-PHASE, STACKABLE CONTROLLER SLUS660A – SEPTEMBER 2005 – REVISED JULY 2006 ELECTRICAL CHARACTERISTICS (continued) T J = –40°C to 85°C, (unless otherwise noted), VVDD = 7 V, VBP5 = 5 V, UVLO_CE1, UCLO_CE2: 10 kΩ, Pullup to BP5, f SW = 300 kHz, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT SENSE AMPLIFIERS (CS1, CS2) Differential input voltage -60 60 mV Input offset voltage CS1, CS2, Trimmed -2.0 0 2.0 mV Ac Gain transfer to PWM COMP 5 mV < VCS < 60 mV, VCSRT = 1.5 V 12 13 14 V/V Input common mode(1) 0 5.8 V CSA Input bias current 100 nA DIFFERENTIAL AMPLIFIER (DIFFO) Gain 1.0 V < VOUT < 5.8 V 0.997 1 1.003 V/V Input Common Mode Range(1) 0 5.8 V Output Source Current(1) VOUT– VVGSNS = 2 V, VDIFFO > 1.98 V, 2 VDD-VOUT > 2 V Output Source Current(1) VOUT– VVGSNS = 2 V, VDIFFO > 2.02 V VDD-VOUT 1 mA =1 V Output Sink Current(1) VOUT– VVGSNS = 2 V, 2 VDIFFO > 2.02 V Unity gain bandwidth(1) 5 8 MHz Input Impedance, non inverting(1) VOUT to GND 60 k Ω Input Impedance, inverting(1) GSNS to DIFFO 60 GATE DRIVERS HDRV1, HDRV2 Source On VBOOT1, VBOOT2 = 5 V, VSW1 = VSW2 = 0 V, 1 2 3 Resistance Sourcing 100 mA HDRV1, HDRV2 Sink On VVREG = 5 V, VSW1 = VSW2 = 0 V, 0.5 1.2 2 Resistance Sinking 100 mA Ω LDRV1, LDRV2 Source On VVREG = 5 V, VSW1 = VSW2 = 0 V, 1 2 3 Resistance Sourcing 100 mA LDRV1, LDRV2 Sink On VVREG = 5V, VSW1 = VSW2 = 0 V, 0.3 0.65 1 Resistance Sinking 100 mA tRISE HDRVx rise time(1) CLOAD= 3.3 nF 25 75 tFALL HDRVx fall time(1) CLOAD= 3.3nF 25 75 tRISE LDRVx rise time(1) CLOAD= 3.3nF 25 75 ns tFALL LDRVx fall time(1) CLOAD= 3.3nF 20 60 Minimum Controllable On-Time CLOAD= 3.3nF 50 OUTPUT UNDERVOLTAGE FAULT VFB relative to VREF -19% -16.5% -14% Undervoltage delay(1) 3 µs CURRENT LIMIT IILIM Output current 18.8 20 21.2 µA POWER GOOD PGOOD transition low threshold VFB rising relative to VREF 10% 12.5% 15% PGOOD transition low threshold VFB falling relative to VREF -15% -12.5% -10% PGOOD trip hysteresis 2% 5% PGOOD Delay(1) 10 µs Low level output voltage, VOL IPGOOD = 4 mA 0.35 0.4 V PGOOD Bias Current VPGOOD= 5.0 V -2 1 2 µA (1) Ensured by design. Not 100% production tested. Submit Documentation Feedback DEVICE RATINGS 5 |
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