Preliminary Technical Data

ADN2892

Rev. PrA | Page 9 of 12

APPLICATIONS INFORMATION

PCB DESIGN GUIDELINES

Proper RF PCB design techniques must be used for optimal

performance.

Power Supply Connections and Ground Planes

Use of one low impedance ground plane is recommended. The

VEE pins should be soldered directly to the ground plane to

reduce series inductance. If the ground plane is an internal

plane and connections to the ground plane are made through

vias, multiple vias can be used in parallel to reduce the series

inductance, especially on Pin 9, which is the ground return for

the output buffers. The exposed pad should be connected to the

GND plane using filled vias so that solder does not leak through

the vias during reflow. Using filled vias under the package

greatly enhances the reliability of the connectivity of the

exposed pad to the GND plane during reflow.

Use of a 10 µF electrolytic capacitor between VCC and VEE is

recommended at the location where the 3.3 V supply enters the

PCB. When using 0.1 µF and 1 nF ceramic chip capacitors, they

should be placed between the IC power supply VCC and VEE,

as close as possible to the ADN2892 VCC pins.

If connections to the supply and ground are made through vias,

the use of multiple vias in parallel helps to reduce series

inductance, especially on Pin 12, which supplies power to the

high speed OUTP/ OUTN output buffers. Refer to the

schematic in Figure 8 for recommended connections.

DRVCC

2

3

4

12

11

10

9

OUTP

OUTN

DRVEE

PIN

NIN

AVEE

C1

C2

C3

C4

VCC

4.7k - 10k

on host board

ADN2882

VCC

To Host Board

RSSI measurement

to ADC

C10

R1

VCC

VCC

VCC

C5

C6

C7 C8

0.1

µF

R2

R3

C9

connect

exposed

pad to

GND

C1-C4, C11: 0.01

µF X5R/X7R dielectric, 0201 case

C5,C7,C9,C10,C12: 0.1

µF X5R/X7R dielectric, 0402 case

C6, C8: 1nF X5R/X7R dielectric, 0201 case

C12

to ADuC7020

Figure 8. Typical ADN2892 Applications Circuit