Electronic Components Datasheet Search |
|
ZL50062 Datasheet(PDF) 20 Page - Zarlink Semiconductor Inc |
|
ZL50062 Datasheet(HTML) 20 Page - Zarlink Semiconductor Inc |
20 / 68 page ZL50062/4 Data Sheet 20 Zarlink Semiconductor Inc. 2.1.6.2 Backplane Output Port Operation of stream data in Connection Mode or Message Mode is determined by the state of the BMM bit of the Backplane Connection Memory and the channel high impedance state is controlled by the BE bit of the Backplane Connection Memory. The data source (i.e. from the Local or Backplane Data Memory) is determined by the BSRC bit of the Backplane Connection Memory. Refer to Section 8.2, Backplane Connection Memory and Section 11.4, Backplane Connection Memory Bit Definition for more details. 2.2 Frame Pulse Input and Master Input Clock Timing The input frame pulse (FP8i) is an 8kHz input signal active for 122ns or 244ns at the frame boundary. The FPW bit in the Control Register must be set according to the applied pulse width. See Pin Description and Table 13, “Control Register Bits” on page 37, for details. The active state and timing of FP8i can conform either to the ST-BUS or to the GCI-Bus as shown in Figure 7, ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates. The ZL50062/64 device will automatically detect whether an ST-BUS or a GCI-Bus style frame pulse is being used for the master frame pulse (FP8i). The output frame pulses (FP8o and FP16o) are always of the same style (ST-BUS or GCI-Bus) as the input frame pulse. The active edge of the input clock (C8i) shall be selected by the state of the Control Register bit C8IPOL. Note that the active edge of ST-BUS is falling edge, which is the default mode of the device, while GCI-Bus uses rising edge as the active edge. Although GCI frame pulse will be automatically detected, to fully conform to GCI-Bus operation, the device should be set to use C8i rising edge as the active edge (by setting bit C8IPOL HIGH) when GCI-Bus is used. For the purposes of describing the device operation, the remaining part of this document assumes the ST-BUS frame pulse format with a single width frame pulse of 122ns and a falling active clock-edge, unless explicitly stated otherwise. In addition, the ZL50062 device provides FP8o, FP16o, C8o and C16o outputs to support external devices which connect to the output ports. The ZL50064 only provides FP8o and C8o outputs. The generated frame pulses (FP8o, FP16o) will be provided in the same format as the master frame pulse (FP8i). The polarity of C8o and C16o, at the frame boundary, can be controlled by the Control Register bit, COPOL. An analog phase lock loop (APLL) is used to multiply the input clock frequency on C8i to generate an internal clock signal operating at 131.072MHz. |
Similar Part No. - ZL50062 |
|
Similar Description - ZL50062 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |