Electronic Components Datasheet Search |
|
ADF4193 Datasheet(PDF) 11 Page - Analog Devices |
|
ADF4193 Datasheet(HTML) 11 Page - Analog Devices |
11 / 28 page ADF4193 Rev. B | Page 11 of 28 THEORY OF OPERATION The ADF4193 is targeted at GSM base station requirements, specifically to eliminate the need for ping-pong solutions. It works based on fast lock, using a wide loop bandwidth during a frequency change and narrowing the loop bandwidth once frequency lock is achieved. Widening the loop bandwidth is achieved by increasing the charge pump current. Switches are included to change the loop filter component values to maintain stability with the changing charge pump current. The narrow loop bandwidth ensures that phase noise and spur specifications are met. A differential charge pump and loop filter topology are used to ensure that the fast lock time benefit from widening the loop bandwidth is maintained when the loop is restored to narrow bandwidth mode for normal operation. REFERENCE INPUT SECTION The reference input stage is shown in Figure 20. Switches S1 and S2 are normally closed, and S3 is normally open. During power- down, S3 is closed, and S1 and S2 are opened to ensure that there is no loading of the REFIN pin. The falling edge of REFIN is the active edge at the positive edge triggered PFD. BUFFER TO R COUNTER REFIN 100k Ω NC S2 S3 NO NC S1 POWER-DOWN CONTROL Figure 20. Reference Input Stage R Counter and Doubler The 4-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). A toggle flip-flop can be optionally inserted after the R counter to give a further divide-by-2. Using this option has the additional advantage of ensuring that the PFD reference clock has a 50/50 mark-space ratio. This ratio gives the maximum separation between the fast lock timer clock, which is generated off the falling edge of the PFD reference, and the rising edge, which is the active edge in the PFD. It is recommended that this toggle flip-flop be enabled for all even R divide values greater than 2. It must be enabled if dividing down a REFIN frequency that is greater than 120 MHz. An optional doubler before the 4-bit R counter can be used for low REFIN frequencies, up to 20 MHz. With these programmable options, reference division ratios from 0.5 to 30 between REFIN and the PFD are possible. RF INPUT STAGE The RF input stage is shown in Figure 21. It is followed by a 2-stage limiting amplifier to generate the CML clock levels needed for the prescaler. Two prescaler options are selectable: a 4/5 and an 8/9. The 8/9 prescaler is selected for N divider values greater than 80. BIAS GENERATOR 1.6V AGND AVDD 500 Ω 500 Ω RFIN– RFIN+ Figure 21. RF Input Stage RF N Divider The RF N divider allows a fractional division ratio in the PLL feedback path. The integer and fractional parts of the division are programmed using separate registers, as shown in Figure 22 and described in the INT, FRAC, and MOD Relationship section. Integer division ratios from 26 to 255 are allowed and a third-order, Σ-Δ modulator interpolates the fractional value between the integer steps. THIRD-ORDER FRACTIONAL INTERPOLATOR FRAC VALUE MOD REG INT REG RF N DIVIDER N = INT + FRAC/MOD FROM RF INPUT STAGE TO PFD N COUNTER Figure 22. Fractional-N Divider INT, FRAC, and MOD Relationship The INT, FRAC, and MOD values, programmed through the serial interface, make it possible to generate RF output frequencies that are spaced by fractions of the PFD reference frequency. The N divider value, shown inside the brackets of the following equation for the RF VCO frequency (RFOUT), is made up of an integer part (INT) and a fractional part (FRAC/MOD): RFOUT = FPFD × [INT + (FRAC/MOD)] where: RFOUT is the output frequency of the external VCO. FPFD is the PFD reference frequency. |
Similar Part No. - ADF4193 |
|
Similar Description - ADF4193 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |