ADL5519-EVALZ datasheet(7/27 Pages) AD

Part #	ADL5519-EVALZ

Description	1 MHz to 10 GHz, 50 dB Dual Log Detector/Controller

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Manufacturer	AD [Analog Devices]

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Preliminary Technical Data

ADL5519

Rev. PrB | Page 7 of 27

Parameter

Conditions

Min

Typ

Max

Unit

Input B to OUTA Isolation

PINHB = −50 dBm, OUTB = OUTBPINHB ± 1 dB

TBD

dB

PINHA = −50 dBm, OUTA = OUTAPINHA ± 1 dB

TBD

dB

OUTPUT INTERFACE

OUT[A, B] (Pins 12, 7), OUT[P, N] (Pins 10, 9)

OUT[A, B] Voltage Range Min

VST[A, B] = TBD RFIN = open RL

≥ 240

Ω to ground

TBD

V

VST[A, B] = 0V RFIN = open RL

≥ 240

Ω to ground

TBD

V

OUT[P, N] output

OUT[A, B] = OUT[P, N]

VLVL

OUT[P, N] Voltage Range Min

FBK[A, B] = TBD RFIN = open RL

≥ 240

Ω to ground

TBD

V

FBK[A, B] = 0V RFIN = open RL

≥ 240

Ω to ground

TBD

V

Source/Sink Current

Output held at 1V to 1% change

2.2

mA

Small Signal Bandwidth

RFIN = −10 dBm, from CLP[A,B] to OUT[A,B]

TBD

MHz

Output Noise

RF Input = 2.2 GHz, –10 dBm, fNOISE = 100 kHz,

CLP[A,B] = open

TBD

nV/

√Hz

Fall Time

Input level = no signal to –10 dBm, 90% to 10%,

CLP[A,B] = 8 pF

TBD

ns

Fall Time

Input level = no signal to –10 dBm, 90% to 10%,

CLP[A,B] = open;

TBD

ns

Rise Time

Input level = −10 dBm to no signal, 10% to 90%,

CLP[A, B] = 8 pF

TBD

ns

Rise Time

Input level = −10 dBm to no signal, 10% to 90%,

CLP[A,B] = open,

TBD

ns

Video Bandwidth (or Envelope

Bandwidth)

50

MHz

SETPOINT INTERFACE

VST[A, B] (Pins 13, 6)

Nominal Input Range

Input level = 0 dBm, measurement mode

0.5

V

Input level = –50 dBm, measurement mode

1.75

V

Logarithmic Scale Factor

−45

dB/V

Logarithmic Intercept

TBD

Input Resistance

Input level = −20 dBm, controller mode, VST[A,B] = 1

V

40

k

Ω

DIFFERENCE LEVEL ADJUST

VLVL (Pin 4)

Voltage Range

OUT[P, N] = FBK[A, B]

TBD

V

OUT[P, N] Voltage Range

OUT[P, N] = FBK[A, B]

TBD

V

Input Impedance

TBD

Ω||pF

TEMPERATURE COMPENSATION

ADJ[A, B] (Pins 17, 2)

Input Resistance

ADJ[A, B] = 0.9 V, sourcing 50 μA

13

k

Ω

Disable Threshold Voltage

ADJ[A, B] = open

VPOS – 0.4

V

VOLTAGE REFERENCE

VREF (Pin 3)

Output Voltage

1.15

V

Temperature Sensitivity

−40

°C < T

A

< +85

°C

TBD

mV/oC

Current Limit Source/Sink

3/3

mA

TEMPERATURE REFERENCE

TEMP (Pin 15)

Output Voltage

1.3

V

Temperature Sensitivity

−40

°C < T

A

< +125

°C

4.5

mV/oC

Current Limit Source/Sink

5/40

mA/uA

POWER-DOWN INTERFACE

Pin PWDN

Logic Level to Enable

Logic LO enables

TBD

V

Logic Level to Disable

Logic HI disables

TBD

V

Input Current

Logic HI PWDN = 5 V

TBD

μA

Logic LO PWDN = 0 V

TBD

μA

Enable Time

PWDN LO to OUTA/OUTB at 100% final value,

CLPA/B = Open, CHPA/B = 10 nF, RF in = 0 dBm

TBD

μs

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