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ADM1192 Datasheet(PDF) 10 Page - Analog Devices |
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ADM1192 Datasheet(HTML) 10 Page - Analog Devices |
10 / 20 page ADM1192 Rev. 0 | Page 10 of 20 VOLTAGE AND CURRENT READBACK The ADM1192 contains the components to allow voltage and current readback over an Inter-IC (I2C) bus. The voltage output of the current sense amplifier and the voltage on the VCC pin are fed into a 12-bit ADC via a multiplexer. The device can be instructed to convert voltage and/or current at any time during operation via an I2C command. When all conversions are complete, the voltage and/or current values can be read out to 12-bit accuracy in two or three bytes. SERIAL BUS INTERFACE Control of the ADM1192 is carried out via the serial system management bus (I2C). This interface is compatible with I2C fast mode (400 kHz maximum). The ADM1192 is connected to this bus as a slave device, under the control of a master device. IDENTIFYING THE ADM1192 ON THE I2C BUS The ADM1192 has a 7-bit serial bus slave address. When the device powers up, it does so with a default serial bus address. The five MSBs of the address are set to 01011; the two LSBs are determined by the state of the ADR pin. There are four different configurations available on the ADR pin that correspond to four different I2C addresses for the two LSBs (see Table 5). This scheme allows four ADM1192 devices to operate on a single I2C. Table 5. Setting I2C Addresses via the ADR Pin ADR Configuration Address Low state 0x68 Resistor to GND 0x69 Floating (unconnected) 0x6A High state 0x6B GENERAL I2C TIMING Figure 18 and Figure 19 show timing diagrams for general read and write operations using the I2C. The I2C specification defines conditions for different types of read and write operations, which are discussed later. The general I2C protocol operates as follows: 1. The master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line, SDA, while the serial clock line, SCL, remains high. This indicates that a data stream follows. All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit slave address (MSB first) plus an R/W bit that determines the direction of the data transfer; that is, whether data is written to or read from the slave device (0 = write, 1 = read). The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. All other devices on the bus now remain idle while the selected device waits for data to be read from it or written to it. If the R/W bit is 0, the master writes to the slave device. If the R/W bit is 1, the master reads from the slave device. 2. Data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period because a low-to- high transition when the clock is high can be interpreted as a stop signal. If the operation is a write operation, the first data byte after the slave address is a command byte. This tells the slave device what to expect next. It can be an instruction, such as telling the slave device to expect a block write, or it can be a register address that tells the slave where subse- quent data is to be written. Because data can flow in only one direction, as defined by the R/W bit, it is not possible to send a command to a slave device during a read operation. Before doing a read operation, it may first be necessary to do a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. 3. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device releases the SDA line during the low period before the ninth clock pulse, but the slave device does not pull it low. This is known as a no acknowledge. The master then takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition. |
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