MC100EP142MNG datasheet(2/13 Pages) ONSEMI

Part #	MC100EP142MNG

Description	3.3 V / 5 V ECL 9-Bit Shift Register

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Manufacturer	ONSEMI [ON Semiconductor]

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MC10EP142, MC100EP142

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2

Figure 1. Pinout: LQFP−32 (Top View)

25

26

27

28

29

30

31

32

15

14

13

12

11

10

9

1234567

8

24

23

22

21

20

19

18

17

16

Q4

Q2

VCC

MR

Q0

D6

Q3

Q1

VEE

VCC

MC10EP142

MC100EP142

VEE

D1

D2

D3

D4

D5

Figure 2. Pinout: QFN−32 (Top View)

32

31

30

29

28

27

26

25

9

10

11

12

13

14

15

16

1

234

5

6

78

24

23

22

21

20

19

18

17

Exposed Pad (EP)

Q4

Q2

VCC

MR

Q0

D6

Q3

Q1

VEE

VCC

VEE

D1

D2

D3

D4

D5

Table 1. PIN DESCRIPTION

Name

I/O

Default State

Description

1,23,24,25,26,

27,29,30,31

D[0:8]

ECL Input

Low

Single−Ended Parallel Data Inputs [0:8]. Internal 75 kW to VEE.

2

S−IN

ECL Input

Low

Noninverted Differential Serial Input. Internal 75 kW to VEE.

3

S−IN

ECL Input

High

Inverted Differential Serial Input. Internal 75 kW to VEE and 36.5 kW to

VCC.

4

CLK0

ECL Input

Low

Noninverted Differential CLK0 Input. Internal 75 kW to VEE.

5

CLK0

ECL Input

High

Inverted Differential CLK0B Input. Internal 75 kW to VEE and 36.5 kW

to VCC.

6

CLK1

ECL Input

Low

Noninverted Differential CLK1 Input. Internal 75 kW to VEE.

7

CLK1

ECL Input

High

Inverted Differential CLK1B Input. Internal 75 kW to VEE and 36.5 kW

to VCC.

8

SEL

ECL Input

Low

Single−Ended Select Logic Input. Internal 75 kW to VEE.

9

MR

ECL Input

Low

Single−Ended Master Reset Logic Input. Internal 75 kW to VEE.

10,11,12,14,1

5,18,19,22

Q0,Q1,Q2,Q3,

Q4,Q5,Q6,Q8

ECL Output

−

Single−Ended parallel Data outputs [0,1,2,3,4,5,6,8]. Typically

Terminated with 50 W to VTT = VCC − 2 V.

13,17,32

VCC

−

Positive supply Voltage. All VCC Pins must be Externally Connected to

Power Supply to Guarantee Proper Operation.

16,28

VEE

−

Negative supply Voltage. All VEE Pins must be Externally connected

to Power Supply to Guarantee Proper Operation.

20

Q7

ECL Output

−

Noninverted Differential parallel/Serial Data Output 7. Typically

Terminated with 50 W to VTT = VCC − 2 V.

21

Q7

ECL Output

−

Inverted Differential parallel/Serial Data Output 7. Typically

Terminated with 50 W to VTT = VCC − 2 V.

1. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.

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