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ADN2813ACPZ-RL7 Datasheet(PDF) 1 Page - Analog Devices |
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ADN2813ACPZ-RL7 Datasheet(HTML) 1 Page - Analog Devices |
1 / 28 page Continuous Rate 10 Mb/s to 1.25 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp ADN2813 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. FEATURES Serial data input: 10 Mb/s to 1.25 Gb/s Exceeds SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 3.3 mV typ Adjustable slice level: ±95 mV Patented clock recovery architecture Loss-of-signal (LOS) detect range: 2.3 mV to 19 mV Independent slice level adjust and LOS detector No reference clock required Loss-of-lock indicator I2C® interface to access optional features Single-supply operation: 3.3 V Low power: 450 mW typ 5 mm × 5 mm 32-lead LFCSP, Pb free APPLICATIONS SONET OC-1/-3/-12 and all associated FEC rates Fibre Channel, GbE, HDTVs WDM transponders Regenerators/repeaters Test equipment Broadband cross-connects and routers GENERAL DESCRIPTION The ADN2813 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 10 Mb/s to 1.25 Gb/s. The ADN2813 automati- cally locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted. This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power fiber optic receiver. The receiver front-end, loss-of-signal (LOS) detector circuit indicates when the input signal level has fallen below a user- adjustable threshold. The LOS detect circuit has hysteresis to prevent chatter at the output. The ADN2813 is available in a compact 5 mm × 5 mm, 32-lead LFCSP. FUNCTIONAL BLOCK DIAGRAM 2 SLICEP/N LOL DATAOUTP/N LOS THRADJ CLKOUTP/N ADN2813 2 VCC VEE CF1 CF2 PIN NIN VREF QUANTIZER VCO PHASE SHIFTER PHASE DETECT FREQUENCY DETECT LOS DETECT DATA RE-TIMING LOOP FILTER LOOP FILTER REFCLKP/N (OPTIONAL) 2 Figure 1. |
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