ADP1710/ADP1711

Rev. 0 | Page 8 of 16

THEORY OF OPERATION

The ADP1710/ADP1711 are low dropout, CMOS linear

regulators that use an advanced, proprietary architecture to

provide high power supply rejection ratio (PSRR) and excellent

line and load transient response with just a small 1 μF ceramic

output capacitor. Both devices operate from a 2.5 V to 5.5 V

input rail and provide up to 150 mA of output current.

Incorporating a novel scaling architecture, ground current is

very low when driving light loads. Ground current in shutdown

mode is typically 100 nA.

REFERENCE

CURRENT LIMIT

THERMAL PROTECT

SHUTDOWN

AND UVLO

GND

OUT

NC/

ADJ/

BYP

NC = NO CONNECT

IN

EN

+

Figure 18. Internal Block Diagram

Internally, the ADP1710/ADP1711 each consist of a reference,

an error amplifier, a feedback voltage divider, and a PMOS pass

transistor. Output current is delivered via the PMOS pass

device, which is controlled by the error amplifier. The error

amplifier compares the reference voltage with the feedback

voltage from the output and amplifies the difference. If the

feedback voltage is lower than the reference voltage, the gate of

the PMOS device is pulled lower, allowing more current to pass

and increasing the output voltage. If the feedback voltage is

higher than the reference voltage, the gate of the PMOS device

is pulled higher, allowing less current to pass and decreasing the

output voltage.

The ADP1710 is available in two versions, one with fixed output

voltage options and one with an adjustable output voltage. The

fixed output voltage option is set internally to one of sixteen

values between 0.75 V and 3.3 V, using an internal feedback

network. The adjustable output voltage can be set to between 0.8

V and 5.0 V by an external voltage divider connected from OUT

to ADJ. The ADP1711 is available with fixed output voltage

options and features a bypass pin, which allows an external

capacitor to be connected, which reduces internal reference

noise. All devices are controlled by an enable pin (EN).

ADJUSTABLE OUTPUT VOLTAGE

(ADP1710 ADJUSTABLE)

The ADP1710 adjustable version can have its output voltage

set over a 0.8 V to 5.0 V range. The output voltage is set by

connecting a resistive voltage divider from OUT to ADJ. The

output voltage is calculated using the equation

(1)

where:

R1 is the resistor from OUT to ADJ.

R2 is the resistor from ADJ to GND.

The maximum bias current into ADJ is 100 nA, so for less

than 0.5% error due to the bias current, use values less than

60 kΩ for R2.

BYPASS CAPACITOR (ADP1711)

The ADP1711 allows for an external bypass capacitor to be

connected to the internal reference, which reduces output

voltage noise and improves power supply rejection. A low

leakage capacitor of 1 nF or greater (10 nF is recommended)

must be connected between the BYP and GND pins.

ENABLE FEATURE

The ADP1710/ADP1711 use the EN pin to enable and disable

the OUT pin under normal operating conditions. As shown in

Figure 19, when a rising voltage on EN crosses the active

threshold, OUT turns on. When a falling voltage on EN crosses

the inactive threshold, OUT turns off.

2

EN

OUT

TIME (1ms/DIV)

Figure 19. ADP1710 Adjustable Typical EN Pin Operation