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ADSP-21371KSZ-ENG Datasheet(PDF) 8 Page - Analog Devices |
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ADSP-21371KSZ-ENG Datasheet(HTML) 8 Page - Analog Devices |
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8 / 48 page  Rev. PrA | Page 8 of 48 | June 2006 ADSP-21371 Preliminary Technical Data Digital Applications Interface (DAI) The digital applications interface (DAI) provides the ability to connect various peripherals to any of the DSPs DAI pins (DAI_P20–1). Programs make these connections using the signal routing unit (SRU), shown in Figure 1. The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be intercon- nected under software control. This allows easy use of the DAI associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with non con- figurable signal paths. The DAI also includes eight serial ports, four precision clock generators (PCG), and an input data port (IDP). The IDP pro- vides an additional input path to the ADSP-21371 core, configurable as either eight channels of I2S serial data, or a sin- gle 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the ADSP-21371’s serial ports. Serial Ports The ADSP-21371 features eight synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices’ AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock and frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel. Serial ports are enabled via 16 programmable and simultaneous receive or transmit pins that support up to 32 transmit or 32 receive channels of audio data when all eight SPORTS are enabled, or eight full duplex TDM streams of 128 channels per frame. The serial ports operate at a maximum data rate of 33M bits/s. Serial port data can be automatically transferred to and from on-chip memory via dedicated DMA channels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT provides two transmit sig- nals while the other SPORT provides the two receive signals. The frame sync and clock are shared. Serial ports operate in five modes: • Standard DSP serial mode •Multichannel (TDM) mode with support for packed I2S mode •I2S mode •Packed I2S mode • Left-justified sample pair mode Left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitted/received—one sample on the high segment of the frame sync, the other on the low segment of the frame sync. Programs have control over var- ious attributes of this mode. Each of the serial ports supports the left-justified sample pair and I2S protocols (I2S is an industry standard interface com- monly used by audio codecs, ADCs and DACs such as the Analog Devices AD183x family), with two data pins, allowing four left-justified sample pair or I2S channels (using two stereo devices) per serial port, with a maximum of up to 32 I2S chan- nels. The serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. For the left-justified sample pair and I2S modes, data- word lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional μ-law or A-law companding selection on a per channel basis. Serial port clocks and frame syncs can be inter- nally or externally generated. The serial ports also contain frame sync error detection logic where the serial ports detect frame syncs that arrive early (for example frame syncs that arrive while the transmission/recep- tion of the previous word is occurring). All the serial ports also share one dedicated error interrupt. S/PDIF Compatible Digital Audio Receiver/Transmitter and Synchronous/Asynchronous Sample Rate Converter The S/PDIF receiver/transmitter has no separate DMA chan- nels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the receiver/transmitter can be formatted as left justified, I2S or right justified with word widths of 16, 18, 20, or 24 bits. The serial data, clock, and frame sync inputs to the S/PDIF receiver/transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources such as the SPORTs, external pins, the precision clock generators (PCGs), or the sample rate converters (SRC) and are controlled by the SRU control registers. The sample rate converter (SRC) contains four SRC blocks and is the same core as that used in the AD1896 192 kHz stereo asynchronous sample rate converter and provides up to 128 dB SNR. The SRC block is used to perform synchronous or asyn- chronous sample rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to con- vert multichannel audio data without phase mismatches. Finally, the SRC is used to clean up audio data from jittery clock sources such as the S/PDIF receiver. Digital Peripheral Interface (DPI) The digital peripheral interface provides connections to two serial peripheral interface ports (SPI), one universal asynchro- nous receiver-transmitter (UART), 12 flags, a two wire interface (TWI), and two general-purpose timers. Serial Peripheral (Compatible) Interface The ADSP-21371 SHARC processor contains two serial periph- eral interface ports (SPIs). The SPI is an industry standard synchronous serial link, enabling the ADSP-21371 SPI compati- ble port to communicate with other SPI compatible devices. The SPI consists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, sup- |
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