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ADSP-BF539 Datasheet(PDF) 9 Page - Analog Devices |
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ADSP-BF539 Datasheet(HTML) 9 Page - Analog Devices |
9 / 68 page ADSP-BF539/ADSP-BF539F Preliminary Technical Data Rev. PrF | Page 9 of 68 | September 2006 register may be read while in supervisor mode and may only be written while in supervisor mode when the corre- sponding IMASK bit is cleared. • CEC Interrupt Mask Register (IMASK) – The IMASK reg- ister controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and will be processed by the CEC when asserted. A cleared bit in the IMASK register masks the event, pre- venting the processor from servicing the event even though the event may be latched in the ILAT register. This register may be read or written while in supervisor mode. (Note that general purpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively.) • CEC Interrupt Pending Register (IPEND) – The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates the event is currently active or nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode. The SIC allows further control of event processing by providing three 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 3 on Page 8. • SIC Interrupt Mask Registers (SIC_IMASKx)– These regis- ters control the masking and unmasking of each peripheral interrupt event. When a bit is set in these registers, that peripheral event is unmasked and will be processed by the system when asserted. A cleared bit in these registers masks the peripheral event, preventing the processor from servic- ing the event. • SIC Interrupt Status Registers (SIC_ISRx) – As multiple peripherals can be mapped to a single event, these registers allow the software to determine which peripheral event source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt, and a cleared bit indi- cates the peripheral is not asserting the event. • SIC Interrupt Wakeup Enable Registers (SIC_IWRx) – By enabling the corresponding bit in these registers, a periph- eral can be configured to wake up the processor, should the core be idled when the event is generated. (For more infor- mation, see Dynamic Power Management on Page 14.) Because multiple interrupt sources can map to a single general purpose interrupt, multiple pulse assertions can occur simulta- neously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND reg- ister contents are monitored by the SIC as the interrupt acknowledgement. The appropriate ILAT register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). The bit is cleared when the respective IPEND register bit is set. The IPEND bit indicates that the event has entered into the proces- sor pipeline. At this point the CEC will recognize and queue the next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the general purpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depend- ing on the activity within and the state of the processor. DMA CONTROLLERS The ADSP-BF539/ADSP-BF539F processor has multiple, inde- pendent DMA controllers that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the ADSP-BF539/ADSP-BF539F processor internal memories and any of its DMA capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA capable peripherals and external devices connected to the external memory interfaces, including the SDRAM con- troller and the asynchronous memory controller. DMA capable peripherals include the SPORTs, SPI port, UART, and PPI. Each individual DMA capable peripheral has at least one dedicated DMA channel. The MXVR peripheral has its own dedicated DMA controller, which supports its own unique set of operating modes. DMA13 Interrupt (SPORT2 TX) IVG9 DMA14 Interrupt (SPORT3 RX) IVG9 DMA15 Interrupt (SPORT3 TX) IVG9 DMA5 Interrupt (SPI0) IVG10 DMA18 Interrupt (SPI1) IVG10 DMA19 Interrupt (SPI2) IVG10 DMA6 Interrupt (UART0 RX) IVG10 DMA7 Interrupt (UART0 TX) IVG10 DMA20 Interrupt (UART1 RX) IVG10 DMA21 Interrupt (UART1 TX) IVG10 DMA22 Interrupt (UART2 RX) IVG10 DMA23 Interrupt (UART2 TX) IVG10 Timer0, Timer1, Timer2 Interrupts IVG11 TWI0 Interrupt IVG11 TWI1 Interrupt IVG11 CAN Receive Interrupt IVG11 CAN Transmit Interrupt IVG11 MXVR Status Interrupt IVG11 MXVR Control Message Interrupt IVG11 MXVR Asynchronous Packet Interrupt IVG11 Programmable Flags Interrupt IVG12 MDMA0 Stream 0 Interrupt IVG13 MDMA0 Stream 1 Interrupt IVG13 MDMA1 Stream 0 Interrupt IVG13 MDMA1 Stream 1 Interrupt IVG13 Software Watchdog Timer IVG13 Table 3. System and Core Event Mapping (Continued) Event Source Core Event Name |
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