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ADT75ARZ-REEL Datasheet(PDF) 6 Page - Analog Devices |
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ADT75ARZ-REEL Datasheet(HTML) 6 Page - Analog Devices |
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6 / 24 page  ADT75 Rev. 0 | Page 6 of 24 TIMING SPECIFICATIONS AND DIAGRAM Measure the SDA and SCL timing with the input filters turned on to meet the fast mode I2C specification. Switching off the input filters improves the transfer rate but has a negative affect on the EMC behavior of the part. TA = TMIN to TMAX, VDD = +2.7 V to +5.5 V, unless otherwise noted. Table 3. Parameter1 MIN TYP MAX Units Comments Serial Clock Period, t1 2.5 μs Fast mode I2C. See Figure 2 Data In Setup Time to SCL High, t2 50 ns See Figure 2 Data Out Stable After SCL Low, t3 0 0.92 ns Fast mode I2C. See Figure 2 Data Out Stable After SCL Low, t3 0 3.452 μs Standard mode I2C. See Figure 2 SDA Low Setup Time to SCL Low (Start Condition), t4 50 ns See Figure 2 SDA High Hold Time After SCL High (Stop Condition), t5 50 ns See Figure 2 SDA and SCL Rise Time, t6 300 ns Fast mode I2C. See Figure 2 SDA and SCL Rise Time, t6 1000 ns Standard mode I2C. See Figure 2 SDA and SCL Fall Time, t7 300 ns See Figure 2 Capacitive Load for each Bus Line, CB 400 pF 1 Guaranteed by design and characterization; not production tested. 2 This time has to be met only if the master does not stretch the low period of the SCL signal. SCL t4 t2 t1 t3 t5 t7 SDA DATA IN SDA DATA OUT t6 Figure 2. SMBus/I2C Timing Diagram |
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