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AD5664RBRMZ-5 Datasheet(PDF) 22 Page - Analog Devices |
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AD5664RBRMZ-5 Datasheet(HTML) 22 Page - Analog Devices |
22 / 28 page AD5624R/AD5644R/AD5664R Rev. A | Page 22 of 28 POWER-ON RESET The AD5624R/AD5644R/AD5664R family contains a power-on reset circuit that controls the output voltage during power-up. The AD5624R/AD5644R/AD5664R DACs output power up to 0 V and the output remains there until a valid write sequence is made to the DACs. This is useful in applications where it is important to know the state of the output of the DACs while they are in the process of powering up. SOFTWARE RESET The AD5624R/AD5644R/AD5664R contain a software reset function. Command 101 is reserved for the software reset function (see Table 8). The software reset command contains two reset modes that are software programmable by setting bit DB0 in the control register. Table 10 shows how the state of the bit corresponds to the software reset modes of operation of the devices. Table 12 shows the contents of the input shift register during the software reset mode of operation. Table 10. Software Reset Modes for the AD5624R/AD5644R/AD5664R DB0 Registers Reset to Zero 0 DAC register Input shift register 1 (Power-On Reset) DAC register Input shift register LDAC register Power-down register Internal reference setup register POWER-DOWN MODES The AD5624R/AD5644R/AD5664R contain four separate modes of operation. Command 100 is reserved for the power-down function (see Table 8). These modes are software programmable by setting two bits (DB5 and DB4) in the control register. Table 11 shows how the state of the bits corresponds to the mode of operation of the device. All DACs, (DAC D to DAC A) can be powered down to the selected mode by setting the corresponding four bits (DB3, DB2, DB1, and DB0) to 1. By executing the same Command 100, any combination of DACs can be powered up by setting the bits (DB5 and DB4) to normal operation mode. To select which combination of DAC channels to power-up, set the corresponding four bits (DB3, DB2, DB1, and DB0) to 1. See Table 13 for contents of the input shift register during power-down/power-up operation. Table 11. Modes of Operation for the AD5624R/AD5644R/ AD5664R DB5 DB4 Operating Mode 0 0 Normal operation Power-down modes 0 1 1 kΩ to GND 1 0 100 kΩ to GND 1 1 Three-state When Bit DB5 and Bit DB4 are set to 0, the part works normally with its normal power consumption of 450 μA at 5 V. However, for the three power-down modes, the supply current falls to 480 nA at 5 V (200 nA at 3 V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This allows the output impedance of the part to be known while the part is in power-down mode. The outputs can either be connected internally to GND through a 1 kΩ resistor, or left open-circuited (three-state) as shown in Figure 54. RESISTOR NETWORK VOUT RESISTOR STRING DAC POWER-DOWN CIRCUITRY AMPLIFIER Figure 56. Output Stage During Power-Down The bias generator, the output amplifier, the resistor string, and other associated linear circuitry are shutdown when power- down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 4 μs for VDD = 5 V and for VDD = 3 V (see Figure 39). Table 12. 24-Bit Input Shift Register Contents for Software Reset Command DB23 to DB22 (MSB) DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DB0 (LSB) x 1 0 1 x x x x 1/0 Don’t care Command bits (C2 to C0) Address bits (A2 to A0) Don’t care Determines software reset mode Table 13. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation for the AD5624R/AD5644R/AD5664R DB23 to DB22 (MSB) DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB) x 1 0 0 x x x x PD1 PD0 DAC D DAC C DAC B DAC A Don’t care Command bits (C2 to C0) Address bits (A2 to A0) Don’t care Don’t care Power-down mode Power-down/power-up channel selection, set bit to 1 to select channel |
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Similar Description - AD5664RBRMZ-5 |
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