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NCP1562ADR2G Datasheet(PDF) 2 Page - ON Semiconductor |
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NCP1562ADR2G Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 26 page NCP1562A, NCP1562B http://onsemi.com 2 Figure 1. Detailed Block Diagram Vin 1 16 VAUX Iinhibit Istart Disable + -- VAUX(on) + -- Central Logic Disable_VREF 5.0 V Reference VAUX P.O.R. Bias VREF 8 S Dominant Reset Latch R Q CAUX VAUX(on)/ VAUX(off1)/ VAUX(off2) + -- + -- One Shot Pulse VUV Soft--Stop Complete Thermal Shutdown STOP UVOV Detector UVOV Vin R2 R1 2V 3V Vref CT RT 6 RTCT 500 mA SYNC DMAX Clock Oscillator 7 SYNC + -- CSKIP Comparator + -- VCSKIP CSKIP Control Logic VREF ICSKIP(C) ICSKIP(D) 12 CSKIP CCSKIP Clock + -- Not Saturated + -- 3.6 V Saturation Comparator S Dominant Reset Latch R Q Q Clock FF Reset Delay Logic Enable_Output OUT1 15 VAUX 14 PGND OUT2 13 VAUX 11 270 kΩ 20 kΩ VREF -- + PWM Comparator -- + Soft--Start Comparator -- + FF Comparator + -- 0.2 V 3V + -- Vin RFF CFF VEA FF 3 5 GND FF Reset Ilimit Comparator + -- + -- 0.2 V = A ver. (0.5 V= Bver.) OUT Fixed80ns LEB Clock Enable Not Saturated Soft--Start Soft--Stop Control Logic STOP VX Soft--Start Complete Soft--Stop Complete VREF ISS(C) ISS(D) 10 SS CSS 4 CS Enable_Output 1V 2 tD RD 9 VX |
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