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AD5627RBRMZ-2 Datasheet(PDF) 7 Page - Analog Devices

Part # AD5627RBRMZ-2
Description  Dual, 12-/14-/16-Bit nanoDACs with 5ppm/C On-Chip Ref, I2C Interface
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5627RBRMZ-2 Datasheet(HTML) 7 Page - Analog Devices

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Preliminary Technical Data
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Rev. PrA. | Page 7 of 30
Limit at TMIN, TMAX
Parameter
Conditions2
Min
Max
Unit
Description
t12
Standard mode
300
ns
tFCL, fall time of SCL signal
Fast mode
300
ns
High speed mode, CB = 100 pF
10
40
ns
High speed mode, CB = 400 pF
20
80
ns
tSP4
Fast mode
0
50
ns
Pulse width of spike suppressed
High speed mode
0
10
ns
1See Figure 2. High speed mode timing specification applies only to the AD5627BRUZ-2 and AD5667BRUZ-2.
2CB refers to the capacitance on the bus line.
3The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the part.
4 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode.
Figure 2. 2-Wire Serial Interface Timing Diagram


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