NCP1582, NCP1582A, NCP1583

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9

results in larger values of output capacitance to maintain

tight output voltage regulation. In contrast, smaller values of

inductance increase the regulator’s maximum achievable

slew rate and decrease the necessary capacitance, at the

expense of higher ripple current. The peak−to−peak ripple

current is given by the following equation:

Ipk

* pkLOUT +

VOUT(1 * D)

LOUT

350 kHz

,

From this equation it is clear that the ripple current increases

dynamic response and ripple current.

Feedback and Compensation

The NCP158x allows the output of the DC−DC converter

to be adjusted from 0.8 V to 5.0 V via an external resistor

divider network. The controller will try to maintain 0.8 V at

the feedback pin. Thus, if a resistor divider circuit was

regulate the output voltage proportional to the resistor

divider network in order to maintain 0.8 V at the FB pin.

R1

R2

FB

The relationship between the resistor divider network

above and the output voltage is shown in the following

equation:

R2 + R1

VREF

VOUT * VREF

.

Resistor R1 is selected based on a design tradeoff between

efficiency and output voltage accuracy. For high values of

R1 there is less current consumption in the feedback

network, However the trade off is output voltage accuracy

due to the bias current in the error amplifier. The output

voltage error of this bias current can be estimated using the

following equation (neglecting resistor tolerance):

Error%

+

0.1

mA

R1

VREF

100%.

Once R1 has been determined, R2 can be calculated.

Figure 12. Type II Transconductance Error

Amplifier

R1

R2

+

EA

Gm

Figure 12 shows a typical Type II transconductance error

amplifier (EOTA). The compensation network consists of

the internal error amplifier and the impedance networks ZIN

compensation network has to provide a closed loop transfer

function with the highest 0 dB crossing frequency to have

gain in DC conditions to minimize the load regulation. A

stable control loop has a gain crossing with −20 dB/decade

slope and a phase margin greater than 45

°. Include

worst−case component variations when determining phase

margin. Loop stability is defined by the compensation

network around the EOTA, the output capacitor, output

inductor and the output divider. Figure 13. shows the open

loop and closed loop gain plots.

Compensation Network Frequency:

The inductor and capacitor form a double pole at the

frequency

FLC +

1

2

p @ LO @ CO

The ESR of the output capacitor creates a “zero” at the

frequency,

FESR +

1

2

p @ ESR @ CO

The zero of the compensation network is formed as,

FZ +

1

2

p @ RCCC

The pole of the compensation network is calculated as,

FP +

1

2

p @ RC @ CP