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ADSP-21366BBC-1AA Datasheet(PDF) 7 Page - Analog Devices |
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ADSP-21366BBC-1AA Datasheet(HTML) 7 Page - Analog Devices |
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7 / 52 page  ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. A | Page 7 of 52 | December 2006 The SRAM can be configured as a maximum of 96K words of 32-bit data, 192K words of 16-bit data, 64K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to three megabits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32- bit floating-point and 16-bit floating-point formats is per- formed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and PM buses, with one bus dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. DMA Controller The ADSP-2136x’s on-chip DMA controllers allow data trans- fers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simulta- neously executing its program instructions. DMA transfers can occur between the processor’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the parallel data acquisition port (PDAP), or the parallel port. Twenty-five channels of DMA are available on the processors—two for the SPI interface, 12 via the serial ports, eight via the input data port, two for DTCP (or memory- to-memory data transfer when DTCP is not used), and one via the processor’s parallel port. Programs can be downloaded to the processors using DMA transfers. Other DMA features include interrupt generation upon completion of DMA trans- fers, and DMA chaining for automatic linked DMA transfers. Digital Audio Interface (DAI) The digital audio interface (DAI) provides the ability to connect various peripherals to any of the DSP’s DAI pins (DAI_P20–1). Programs make these connections using the signal routing unit (SRU, shown in Figure 3). The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be intercon- nected under software control. This allows easy use of the DAI- associated peripherals for a much wider variety of applica- tions by using a larger set of algorithms than is possible with nonconfigurable signal paths. The DAI also includes six serial ports, an S/PDIF receiver/trans- mitter, a DTCP cipher, a precision clock generator (PCG), eight channels of asynchronous sample rate converters, an input data port (IDP), an SPI port, six flag outputs and six flag inputs, and Reserved 0x0007 2000–0x0007 FFFF Reserved 0x000E 4000–0x000F FFFF Reserved 0x001C 8000–0x001F FFFF Reserved 0x0020 0000–0xFFFF FFFF Table 3. ADSP-2136x Internal Memory Space (Continued) IOP Registers 0x0000 0000–0003 FFFF Long Word (64 Bits) Extended Precision Normal or Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits) Figure 3. ADSP-2136x I/O Processor and Peripherals Block Diagram 16 3 PRECISION CLOCK GENERATORS (2) SPI PORT (1) 4 SERIAL PORTS (6) INPUT DATA PORTS (8) TIMERS (3) 3 DMA CONTROLLER PARALLEL PORT 4 GPIO FLAGS/IRQ/TIMEXP ADDRESS/DATA BUS/ GPIO CONTROL/GPIO DIGITAL AUDIO INTERFACE 25 CHANNELS TO PROCESSOR BUSES AND SYSTEM MEMORY IO ADDRESS BUS (18) SRC (8 CHANNELS) SPDIF (Rx/Tx) DTCP CIPHER PWM (16) IO DATA BUS (32) SPI PORT (1) 4 20 I/O PROCESSOR |
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