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AD7641BCPZ Datasheet(PDF) 6 Page - Analog Devices |
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AD7641BCPZ Datasheet(HTML) 6 Page - Analog Devices |
6 / 14 page AD7631/AD7634 Preliminary Technical Data Rev. PrC | Page 6 of 14 TIMING SPECIFICATIONS AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15V; VEE = -15V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Symbol Min Typ Max Unit CONVERSION AND RESET Convert Pulse Width t1 10 ns Time Between Conversions (Warp Mode/Normal Mode1) t2 ns AD7631 4 μs AD7634 (Warp Mode/Normal Mode/Impulse Mode)2 1.49/1.75/2.22 μs CNVST Low to BUSY High Delay t3 35 ns BUSY High All Modes (Except Master Serial Read After Convert) t4 AD7631 TBD μs AD7634 (Warp Mode/Normal Mode/Impulse Mode) TBD μs Aperture Delay t5 2 ns End of Conversion to BUSY Low Delay t6 10 ns Conversion Time t7 AD7631 TBD μs AD7634 (Warp Mode/Normal Mode/Impulse Mode) TBD μs Acquisition Time t8 AD7631 250 ns AD7634 (Warp Mode/Normal Mode/Impulse Mode) 250 ns RESET Pulse Width t9 10 ns PARALLEL INTERFACE MODES CNVST Low to DATA Valid Delay t10 AD7631 1.5 μs AD7634 (Warp Mode/Normal Mode/Impulse Mode) 1/1.25/1.5 μs DATA Valid to BUSY Low Delay t11 12 ns Bus Access Request to DATA Valid t12 45 ns Bus Relinquish Time t13 5 15 ns MASTER SERIAL INTERFACE MODES3 CS Low to SYNC Valid Delay t14 10 ns CS Low to Internal SCLK Valid Delay t15 10 ns CS Low to SDOUT Delay t16 10 ns CNVST Low to SYNC Delay t17 AD7631 525 ns AD7634 (Warp Mode/Normal Mode/Impulse Mode) 25/275/525 ns SYNC Asserted to SCLK First Edge Delay t18 3 ns Internal SCLK Period4 t19 25 40 ns Internal SCLK High4 t20 12 ns Internal SCLK Low4 t21 7 ns SDOUT Valid Setup Time4 t22 4 ns SDOUT Valid Hold Time4 t23 2 ns SCLK Last Edge to SYNC Delay4 t24 3 ns CS High to SYNC HI-Z t25 10 ns CS High to Internal SCLK HI-Z t26 10 ns CS High to SDOUT HI-Z t27 10 ns |
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