P89LPC9408 datasheet(8/69 Pages) PHILIPS

Part #	P89LPC9408

Description	8-bit microcontroller with two-clock 80C51 core 8 kB 3 V byte-erasable flash, 32 segment x 4 LCD driver, 10-bit ADC

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Manufacturer	PHILIPS [NXP Semiconductors]

Direct Link	http://www.nxp.com

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8 / 69 page

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

8 of 69

Philips Semiconductors

P89LPC9408

8-bit two-clock 80C51 core with 32 segment

× 4 LCD driver, 10-bit ADC

P1.2/T0/SCL

17

I/O

P1.2 — Port 1 bit 2 (open-drain when used as output).

I/O

T0 — Timer/counter 0 external count input or overﬂow output (open-drain when used

as output).

I/O

SCL — I2C-bus serial clock input/output.

P1.3/INT0/

SDA

16

I/O

P1.3 — Port 1 bit 3 (open-drain when used as output).

I

INT0 — External interrupt 0 input.

I/O

SDA — I2C-bus serial data input/output.

P1.4/INT1

15

I

P1.4 — Port 1 bit 4.

I

INT1 — External interrupt 1 input.

P1.5/RST

11

I

P1.5 — Port 1 bit 5 (input only).

I

RST — External Reset input during power-on or if selected via UCFG1. When

functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O

ports and peripherals to take on their default states, and the processor begins

execution at address 0. Also used during a power-on sequence to force ISP mode.

When using an oscillator frequency above 12 MHz, the reset input function of

P1.5 must be enabled. An external circuit is required to hold the device in reset at

power-up until VDD has reached its speciﬁed level. When system power is

removed VDD will fall below the minimum speciﬁed operating voltage. When

using an oscillator frequency above 12 MHz, in some applications, an external

brownout detect circuit may be required to hold the device in reset when VDD falls

below the minimum speciﬁed operating range.

P1.6/OCB

10

I/O

P1.6 — Port 1 bit 6.

O

OCB — Output Compare B.

P1.7/OCC/

AD04

9

I/O

P1.7 — Port 1 bit 7.

O

OCC — Output Compare C.

I

AD04 — ADC0 channel 4 analog input.

P2.0 to P2.3,

P2.5

I/O

Port 2: Port 2 is an 5-bit I/O port with a user-conﬁgurable output type. During reset

Port 2 latches are conﬁgured in the input only mode with the internal pull-up disabled.

The operation of Port 2 pins as inputs and outputs depends upon the port conﬁguration

selected. Each port pin is conﬁgured independently. Refer to Section 7.13.1 “Port

conﬁgurations” and Table 12 “Static electrical characteristics” for details.

All pins have Schmitt trigger inputs.

Port 2 also provides various special functions as described below:

P2.0/ICB/

AD07

6

I/O

P2.0 — Port 2 bit 0.

I

ICB — Input Capture B.

I

AD07 — ADC0 channel 7 analog input.

P2.1/OCD/

AD06

7

I/O

P2.1 — Port 2 bit 1.

O

OCD — Output Compare D.

I

AD06 — ADC0 channel 6 analog input.

P2.2/MOSI

18

I/O

P2.2 — Port 2 bit 2.

I/O

MOSI — SPI master out slave in. When conﬁgured as master, this pin is output; when

conﬁgured as slave, this pin is input.

P2.3/MISO

19

I/O

P2.3 — Port 2 bit 3.

I/O

MISO — When conﬁgured as master, this pin is input, when conﬁgured as slave, this

pin is output.

Table 3:

Pin description …continued

Symbol

Type Description

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