AD9704 datasheet(1/52 Pages) AD

Part #	AD9704

Description	8-/10-/12-/14-Bit, 175 MSPS TxDAC D/A Converters

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8-/10-/12-/14-Bit, 175 MSPS

TxDAC® D/A Converters

AD9704/AD9705/AD9706/AD9707

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other

rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

FEATURES

Pin-compatible family

Low power member of pin-compatible

TxDAC product family

Power dissipation @ 3.3 V

22 mW @ 10 MSPS

25 mW @ 25 MSPS

30 mW @ 50 MSPS

Sleep mode: 3.1 mW @ 3.3 V

Supply voltage: 1.7 V to 3.6 V

SFDR to Nyquist

AD9707: 84 dBc @ 5 MHz output

AD9707: 83 dBc @ 10 MHz output

AD9707: 75 dBc @ 20 MHz output

AD9707 NSD @ 10 MHz output, 125 MSPS: −147 dBc/Hz

Differential current outputs: 1 mA to 5 mA

Data format: twos complement or straight binary

On-chip 1.0 V reference

CMOS-compatible digital interface

Edge-triggered latches

Clock input: single-ended and differential

Output common mode: adjustable 0 V to 1.2 V

Power-down mode < 2 mW @ 3.3 V (SPI® controllable)

Serial peripheral interface (SPI)

Self-calibration

32-lead LFCSP_VQ, Pb-free package

FUNCTIONAL BLOCK DIAGRAM

0.1µF

LSB

SWITCHES

SEGMENTED

SWITCHES

LATCHES

CURRENT

SOURCE

ARRAY

DIGITAL INPUTS (DB13 TO DB0) SLEEP/CSB

CMODE/SCLK

MODE/SDIO

SPI

IOUTB

IOUTA

OTCM

REFIO

FS ADJ

CLKVDD

CLKCOM

CLK–

CLK+

ACOM

AVDD

DVDD

DCOM

1.0V REF

RSET

1.7V TO 3.6V

1.7V

TO

3.6V

1.7V TO

3.6V

PIN/SPI/RESET

AD9707

Figure 1. AD9707

PRODUCT HIGHLIGHTS

1.

Pin Compatible. The AD970x line of TxDACs is pin-

compatible with the AD974x TxDAC line (LFCSP_VQ

package).

2.

Low Power. Complete CMOS DAC operates on a single

supply of 3.6 V down to 1.7 V, consuming 25 mW (3.3 V)

and 10 mW (1.8 V). The DAC full-scale current can be

reduced for lower power operation, and sleep and power-

down modes are provided for low power idle periods.

3.

Self-calibration. Self-calibration enables true 14-bit INL

and DNL performance in the AD9707.

4.

Twos Complement/Binary Data Coding Support. Data input

supports twos complement or straight binary data coding.

5.

CMOS Clock Input. High speed, single-ended, and

differential CMOS clock input supports 175 MSPS

conversion rate.

6.

SPI Control. SPI control offers a higher level of

programmability.

7.

Easy Interfacing to Other Components. Adjustable output

common mode from 0 V to 1.2 V allows for easy interfacing

to other components that accept common-mode levels

greater than 0 V.

8.

On-Chip Voltage Reference. The AD970x includes a 1.0 V

temperature-compensated band gap voltage reference.

9.

Industry-Standard 32-Lead LFCSP_VQ Package.

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