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KM62U256DLTG-10L Datasheet(PDF) 5 Page - Samsung semiconductor |
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KM62U256DLTG-10L Datasheet(HTML) 5 Page - Samsung semiconductor |
5 / 9 page KM62V256D, KM62U256D Family CMOS SRAM Revision 1.0 November 1997 5 CL1) 1. Including scope and jig capacitance AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level : 0.4 to 2.4V Input rising and falling time : 5ns Input and output reference voltage : 1.5V Output load (See right) :CL=100pF+1TTL CL1)=30pF+1TTL 1. Refer to AC CHARACTERISTICS AC CHARACTERISTICS (KM62V256D Family:Vcc=3.0~3.6V, KM62U256D Family:Vcc=2.7~3.3V Commercial product :TA=0 to 70 °C, Extended product :TA=-25 to 85°C, Industrial product :TA=-40 to 85°C) 1. The parameter is measured with 30pF test load Parameter List Symbol Speed Bins Units 701)ns 85ns 100ns Min Max Min Max Min Max Read Read cycle time tRC 70 - 85 - 100 - ns Address access time tAA - 70 - 85 - 100 ns Chip select to output tCO - 70 - 85 - 100 ns Output enable to valid output tOE - 35 - 40 - 50 ns Chip select to low-Z output tLZ 10 - 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - 5 - ns Chip disable to high-Z output tHZ 0 30 0 30 0 35 ns Output disable to high-Z output tOHZ 0 30 0 30 0 35 ns Output hold from address tOH 5 - 10 - 15 - ns Write Write cycle time tWC 70 - 85 - 100 - ns Chip select to end of write tCW 60 - 70 - 80 - ns Address set-up time tAS 0 - 0 - 0 - ns Address valid to end of write tAW 60 - 70 - 80 - ns Write pulse width tWP 50 - 60 - 70 - ns Write recovery time tWR 0 - 0 - 0 - ns Write to output high-Z tWHZ 0 25 0 25 0 35 ns Data to write time overlap tDW 30 - 35 - 40 - ns Data hold from write time tDH 0 - 0 - 0 - ns End write to output low-Z tOW 5 - 10 - 10 - ns DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Min Typ Max Unit Vcc for data retention VDR CS ≥Vcc-0.2V 2.0 - 3.6 V Data retention current IDR Vcc=3.0V, CS ≥Vcc-0.2V - 5 µA Data retention set-up time tSDR See data retention waveform 0 - - ms Recovery time tRDR 5 - - |
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