Low EMI Clock Generator for Intel
810E Chipset Systems
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07053 Rev. **
05/03/01
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
Page 7 of 18
http://www.cypress.com
APPROVED PRODUCT
C9812
Serial Control Registers
NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true
power up. Bytes are set to the values shown only on true power up.
Following the acknowledge of the Address Byte, two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte.
Although the data (bits) in these two bytes are considered “don’t care”; they must be sent and will be acknowledged.
After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte 0, Byte 1,
and Byte2) will be valid and acknowledged.
Byte 0: CPU Clock Register (1=Enable, 0=Disable, Default=07)
Bit
@Pup
Pin#
Description
7
0
-
Reserved
6
0
-
Reserved
5
0
-
Reserved
4
0
-
Reserved
3
0
-
Spread spectrum mode
21
26
DOT
11
25
USB
0
1
49
CPU2_ITP
Byte 2: PCI Clock Register (1=Enable, 0=Disable, Default=FE)
Bit
@Pup
Pin#
Description
71
20
PCI7
61
19
PCI6
51
18
PCI5
41
16
PCI4
31
15
PCI3
21
13
PCI2
11
12
PCI1
0
0
-
Reserved
Byte 1: SDRAM Clock Register (1=Enable, 0=Disable, Default=FF)
Bit
@Pup
Pin#
Description
7
1
36
SDRAM7
6
1
37
SDRAM6
5
1
39
SDRAM5
4
1
40
SDRAM4
3
1
42
SDRAM3
2
1
43
SDRAM2
1
1
45
SDRAM1
0
1
46
SDRAM0
Byte 3: Reserved Register (Default=00)
Byte 4: Reserved Register (Default=00)
Byte 5: SSCG Control Register (Default=00)
Bit
@Pup
Pin#
Description
7
0
-
Spread Mode (0=down, 1=center)
6
0
-
Ref. Table 4
5
0
-
Ref. Table 4
4
0
-
Reserved
3
0
-
Reserved
2
0
-
Reserved
1
0
-
Reserved
0
0
-
Reserved
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