6.42

IDT709199L

High-Speed 128K x 9 Synchronous Pipelined Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

8

Timing Waveform of Read Cycle for

Timing Waveform of Read Cycle for Pipelined Operation

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2.

OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.

3.

4. The output is disabled (High-Impedance state) by

5. Addresses do not have to be accessed sequentially since

are for reference use only.

6. "X" here denotes Left or Right port. The diagram is with respect to that port.

An

An + 1

An + 2

An + 3

R/

W

ADDRESS

CLK

OE

Qn

Qn + 1

Qn + 2

4847 drw 07

(1)

(1)

(1)

(1)

(2)

(4)

(5)

An

An + 1

An + 2

An + 3

R/

W

ADDRESS

CLK

(4)

OE

Qn

Qn + 1

Qn + 2

4847 drw 08

(1)

(1)

(1)

(2)

(5)

(1 Latency)

(6)