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TMS320DM6441ZWT Datasheet(PDF) 8 Page - Texas Instruments |
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TMS320DM6441ZWT Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 229 page  www.ti.com 2.2 Device Compatibility 2.3 ARM Subsystem 2.3.1 ARM926EJ-S RISC CPU TMS320DM6441 Digital Media System-on-Chip SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007 Table 2-1. Characteristics of the Processor (continued) HARDWARE FEATURES DM6441 Core (V) 1.05 V, 1.2 V Voltage I/O (V) 1.8 V, 3.3 V, 1.2 V CLKIN frequency multiplier PLL Options x1 (bypass), x15 (1.05 V), x19 (1.2 V) (27 MHz reference) BGA Package 16 x 16 mm 361-pin BGA (ZWT) Process Technology µm 0.09 µm Product Preview (PP), Product Status(1) Advance Information (AI), PD Production Data (PD) (1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc. The C64x+ DSP core is code-compatible with the C6000™ DSP platform and supports features of the C64x DSP family. The ARM subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is responsible for configuration and control of the device; including the DSP subsystem, the VPSS subsystem, and a majority of the peripherals and external memories. The ARM subsystem includes the following features: • ARM926EJ-S RISC processor • ARMv5TEJ (32/16-bit) instruction set • Little endian • Coprocessor 15 (CP15) • MMU • 16KB instruction cache • 8KB data cache • Write buffer • 16KB internal RAM (32-bit wide access) • 8KB internal ROM (ARM bootloader for non-EMIFA boot options) • Embedded trace module and embedded trace buffer (ETM/ETB) • ARM interrupt controller • PLL controller • Power and sleep controller (PSC) • System module The ARM subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. Specifically, the ARM926EJ-S processor supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes, providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code overhead. Device Overview 8 Submit Documentation Feedback |
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