Electronic Components Datasheet Search |
|
SN74AUP1G80 Datasheet(PDF) 2 Page - Texas Instruments |
|
|
SN74AUP1G80 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 14 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) D CLK Q CLK D Q SN74AUP1G80 LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP SCES593B – JULY 2004 – REVISED JULY 2005 This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING(2) NanoStar™ – WCSP (DSBGA) SN74AUP1G80YEPR 0.23-mm Large Bump – YEP Reel of 3000 _ _ _HX_ NanoFree™ – WCSP (DSBGA) SN74AUP1G80YZPR 0.23-mm Large Bump – YZP (Pb-free) –40 °C to 85°C Reel of 3000 SN74AUP1G80DBVR SOT (SOT-23) – DBV H80_ Reel of 250 SN74AUP1G80DBVT Reel of 3000 SN74AUP1G80DCKR SOT (SC-70) – DCK HX_ Reel of 250 SN74AUP1G80DCKT (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. (2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ⋅ = Pb-free). FUNCTION TABLE INPUTS OUTPUT Q CLK D ↑ H L ↑ L H L or H X Q 0 LOGIC DIAGRAM (POSITIVE LOGIC) 2 |
Similar Part No. - SN74AUP1G80 |
|
Similar Description - SN74AUP1G80 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |