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ISL12027IV27Z Datasheet(PDF) 5 Page - Intersil Corporation |
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ISL12027IV27Z Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 28 page 5 FN8232.4 October 18, 2006 Watchdog Timer/Low Voltage Reset Parameters SYMBOL PARAMETER CONDITIONS MIN TYP (Note 5) MAX UNITS NOTES tRPD VDD Detect to RESET LOW 500 ns 9 tPURST Power-up Reset Time-Out Delay 100 250 400 ms VRVALID Minimum VDD for Valid RESET Output 1.0 V VRESET ISL12027-4.5A Reset Voltage Level 4.59 4.64 4.69 V ISL12027 Reset Voltage Level 4.33 4.38 4.43 V ISL12027-3 Reset Voltage Level 3.04 3.09 3.14 V ISL12027-2.7A Reset Voltage Level 2.87 2.92 2.97 V ISL12027-2.7 Reset Voltage Level 2.58 2.63 2.68 V tWDO Watchdog Timer Period 32.768kHz crystal between X1 and X2 1.70 1.75 1.801 s 725 750 775 ms 225 250 275 ms tRST Watchdog Timer Reset Time-Out Delay 32.768kHz crystal between X1 and X2 225 250 275 ms tRSP I2C Interface Minimum Restart Time 1.2 µs EEPROM SPECIFICATIONS EEPROM Endurance >2,000,000 Cycles EEPROM Retention Temperature ≤75°C 50 Years Serial Interface (I2C) Specifications SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES VIL SDA, and SCL Input Buffer LOW Voltage SBIB = 1 (Under VDD mode) -0.3 0.3 x VDD V VIH SDA, and SCL Input Buffer HIGH Voltage SBIB = 1 (Under VDD mode) 0.7 x VDD VDD + 0.3 V Hysteresis SDA and SCL Input Buffer Hysteresis SBIB = 1 (Under VDD mode) 0.05 x VDD V VOL SDA Output Buffer LOW Voltage IOL = 4mA 0 0.4 V ILI Input Leakage Current on SCL VIN = 5.5V 0.1 10 µA ILO I/O Leakage Current on SDA VIN = 5.5V 0.1 10 µA TIMING CHARACTERISTICS fSCL SCL Frequency 400 kHz tIN Pulse Width Suppression Time at SDA and SCL Inputs Any pulse narrower than the max spec is suppressed. 50 ns tAA SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window. 900 ns tBUF Time the Bus Must be Free Before the Start of a New Transmission SDA crossing 70% of VDD during a STOP condition, to SDA crossing 70% of VDD during the following START condition. 1300 ns tLOW Clock LOW Time Measured at the 30% of VDD crossing. 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VDD crossing. 600 ns ISL12027 |
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