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VFC320BM Datasheet(PDF) 2 Page - Texas Instruments |
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VFC320BM Datasheet(HTML) 2 Page - Texas Instruments |
2 / 12 page VFC320 2 SBVS017A ✻ Specification the same as for VFC320BP. ELECTRICAL CHARACTERISTICS At TA = +25°C and ±15VDC power supply, unless otherwise noted. NOTES: (1) A 25% duty cycle at full scale (0.25mA input current) is recommended where possible to achieve best linearity. (2) Determined by R IN and full scale current range constraints. (3) Adjustable to zero. See Offset and Gain Adjustment section. (4) Linearity error at any operating frequency is defined as the deviation from a straight line drawn between the full scale frequency and 0.1% of full scale frequency. See Discussion of Specifications section. (5) When offset and gain errors are nulled, at an operating temperature, the linearity error determines the final accuracy. (6) For e 1 = 0 typical linearity errors are: 0.01% at 10kHz, 0.2% at 100kHz, 0.1% at 1MHz. (7) Exclusive of external components’ drift. (8) FSR = Full Scale Range (corresponds to full scale and full scale input voltage.) (9) Positive drift is defined to be increasing frequency with increasing temperature. (10) One pulse of new frequency plus 50ns typical. VFC320BP VFC320CP PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS V/F CONVERTER fOUT = VIN/7.5 R1C1, Figure 4 INPUT TO OP AMP Voltage Range(1) Fig. 4 with e2 = 0 >0 Note 2 V Fig. 4 with e1 = 0 <0 –10 V Current Range(1) IIN = VIN/RIN +0.25 +750 ✻✻ µA Bias Current Inverting Input 48 ✻✻ nA Noninverting Input 10 30 ✻✻ nA Offset Voltage(3) ±0.15 ✻ mV Offset Voltage Drift ±5 ✻ µV/°C Differential Impedance 300 || 5 650 || 5 ✻✻ k Ω || pF Common-Mode Impedance 300 || 3 500 || 3 ✻✻ k Ω || pF ACCURACY Linearity Error(1) (4) (5) Fig. 4 with e2 = 0(6) 0.01Hz ≤ f OUT ≤ 10kHz ±0.004 ±0.005 ±0.0015 ±0.002 % FSR 0.1Hz ≤ f OUT ≤ 100kHz ±0.008 ±0.030 ✻✻ % FSR 1Hz ≤ f OUT ≤ 1MHz ±0.1 ✻ % FSR Offset Error Input Offset Voltage(3) ±15 ✻ ppm FSR Offset Drift(7) ±0.5 ✻ ppm FSR/ °C Gain Error(3) ±5 ±10 ✻✻ % FSR Gain Drift(7) f = 10kHz 50 20 ppm FSR/ °C Full Scale Drift f = 10kHz 50 20 ppm FSR/ °C (Offset Drift and Gain Drift)(7)(8)(9) Power Supply Sensitivity ±V CC = 14VDC to 18VDC ±0.015 ✻ % FSR% DYNAMIC RESPONSE Full Scale Frequency CLOAD ≤ 50pF 1 ✻ MHz Dynamic Range 6 ✻ Decades Settling Time (V/F) to Specified Linearity For a Full Scale Input Step Note 10 ✻ Overload Recovery <50% Overload Note 10 ✻ OPEN COLLECTOR OUTPUT Voltage, Logic “0” ISINK = 8mA, max 0.4 ✻ V Leakage Current, Logic “1” VO = 15V 0.01 1.0 ✻✻ µA Voltage, Logic “1” External Pull-up Resistor Required (See Figure 4) VPU ✻ V Duty Cycle at FS For Best Linearity 25 ✻ % Fall Time IOUT = 5mA, CLOAD = 500pF 100 ✻ ns F/V CONVERTER VOUT = 7.5 R1C1 fIN, Figure 9 INPUT TO COMPARATOR Impedance 50 || 10 150 || 10 ✻✻ k Ω || pF Logic “1” +1.0 +VCC ✻✻ V Logic “0”–VCC –0.05 ✻✻ V Pulse-width Range 0.25 ✻ µs OUTPUT FROM OP AMP Voltage IO = 6mA 0 to +10 ✻ V Current VO = 7VDC +10 ✻ mA Impedance Closed-Loop 0.1 ✻ Ω Capacitive Load Without Oscillation 100 ✻ pF POWER SUPPLY Rated Voltage ±15 ✻ V Voltage Range ±13 ±20 ✻✻ V Quiescent Current ±6.5 ±7.5 ✻✻ mA TEMPERATURE RANGE Specification B and C Grades –25 +85 ✻✻ °C S Grade –55 +125 °C Operating B and C Grades –40 +85 ✻✻ °C S Grade –55 +125 °C Storage –65 +150 ✻✻ °C |
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