VFC320CM1 datasheet(6/12 Pages) TI

Part #	VFC320CM1

Description	Voltage-to-Frequency and Frequency-to-Voltage CONVERTER

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Manufacturer	TI [Texas Instruments]

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VFC320

6

SBVS017A

I

IN max

The operation of the VFC320 as a highly linear frequency-

to-voltage converter, follows the same theory of operation as

the voltage-to-frequency converter. e1 and e2 are shorted and

FIN is disconnected from VOUT. FIN is then driven with a

signal which is sufficient to trigger comparator A. The one-

shot period will then be determined by C1 as before, but the

cycle repetition frequency will be dictated by the digital

input at FIN.

DUTY CYCLE

The duty cycle (D) of the VFC is the ratio of the one-shot

period (t2) or pulse width, PW, to the total VFC period (t1 +

t2). For the VFC320, t2 is fixed and t1 + t2 varies as the input

voltage. Thus the duty cycle, D, is a function of the input

voltage. Of particular interest is the duty cycle at full scale

frequency, DFS, which occurs at full scale input. DFS is a user

determined parameter which affects linearity.

D

t

tt

PW f

FS

=

+

=•

2

12

Best linearity is achieved when DFS is 25%. By reducing

equations (7) and (9) it can be shown that

DFS =

=

Thus DFS = 0.25 corresponds to IIN max = 0.25mA.

INSTALLATION AND

OPERATING INSTRUCTIONS

VOLTAGE-TO-FREQUENCY CONVERSION

The VCF320 can be connected to operate as a V/F converter

that will accept either positive or negative input voltages, or

an input current. Refer to Figures 6 and 7.

FIGURE 7. Connection Diagram for V/F Conversion,

Negative Input Voltages.

EXTERNAL COMPONENT SELECTION

In general, the design sequence consists of: (1) choosing

fMAX, (2) choosing the duty cycle at full scale (DFS = 0.25

typically), (3) determining the input resistor, R1 (Figure 4),

(4) calculating the one-shot capacitor, C1, (5) selecting the

integrator capacitor C2, and (6) selecting the output pull-up

resistor, R2.

Input Resistors R1 and R3

The input resistance (R1 and R3 in Figures 6 and 7) is

calculated to set the desired input current at full scale input

voltage. This is normally 0.25mA to provide a 25% duty

cycle at full scale input and output. Values other than DFS =

0.25 may be used but linearity will be affected.

The nominal value is R1 is

R1 =

If gain trimming is to be done, the nominal value is reduced

by the tolerance of C1 and the desired trim range. R1 should

have a very-low temperature coefficient since its drift adds

directly to the errors in the transfer function.

One-Shot Capacitor, C1

This capacitor determines the duration of the one-shot pulse.

From equation (9) the nominal value is

C1 NOM =

For the usual 25% duty at fMAX = VIN/R1 = 0.25mA there is

approximately 15pF of residual capacitance so that the

design value is

C1(pF) =

– 15

(11)

(12)

(10)

V

IN max / R1

1mA

0.25mA

V

INmax

V

IN

7.5 R

1 fOUT

33 • 106

f

FS

1

2

3

4

5

6

7

14

13

12

11

10

9

8

Input

Amp

One-

shot

NC

–V

CC

(1)

NC

+V

CC

(1)

V

IN

C

2

Integrator Capacitor

Gain Adjustment

I

IN

R

3

R

1

R

5

R

4

+15V

–15V

One-shot

Capacitor

C

1

R

2

+V

PU

f

OUT

NOTE: (1) Bypass with 0.01µF

Pin numbers in squares

refer to DIP package.

Offset Adj.

FIGURE 6. Connection Diagram for V/F Conversion,

Positive Input Voltages.

1

2

3

4

5

6

7

14

13

12

11

10

9

8

Input

Amp

One-

shot

NC

–V

CC

(1)

NC

+V

CC

(1)

C

2

Integrator Capacitor

Gain Adjustment

I

IN

R

1

R

3

R

5

R

4

+15V

–15V

One-shot

capacitor

C

1

R

2

+V

PU

f

OUT

NOTE: (1) Bypass with 0.01µF

Pin numbers in squares

refer to DIP package.

Offset Adj.

V

IN

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