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HDSP2113S Datasheet(PDF) 9 Page - Infineon Technologies AG |
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HDSP2113S Datasheet(HTML) 9 Page - Infineon Technologies AG |
9 / 13 page 2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA HDSP2110S/1S/2S/3S/4S/5S www.infineon.com/opto • 1-888-Infineon (1-888-463-4636) OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany www.osram-os.com • +49-941-202-7178 9 March 24, 2000-13 Control Word The Control Word is used to set up the attributes required by the user. It is addressed by setting FL=1, A4=1, A3=0. The Control Word is an 8 bit register and is accessed using data bits, D7–D0. See Figures 12 and 13 for the logic and attributed control. The Control Word has 5 functions. They are brightness control, flashing character enable, blinking character enable, self test, and clear (Flash and Character RAMS only). Brightness Control Control Word bits, D2–D0, control the brightness of the display with a binary code of 000 being 100% brightness and 111 being display blank. See Figure 13 for brightness level versus binary code. The average ICC can be calculated by multiplying the 100% brightness level ICC value by the display’s brightness level. For example, a display set to 80% brightness with a 100% average ICC value of 200 mA will have an average ICC value of 200 mA x 80%=160 mA. Flash Function Control Word bit, D3, enables or disables the Flash Function. When D3 is 1, the Flash Function is enabled and any digit with its corresponding bit set in the Flash RAM will flash at approxi- mately 2.0 Hz. When using an external clock, the flash rate can be determined by dividing the clock rate by 28,672. When D3 is 0, the Flash Function is disabled and the contents of the Flash RAM is ignored. For synchronized flashing on multiple displays, see the Reset Section. UDC Address Register The UDC Address Register is selected by setting FL=1, A4=0, A3=0. It is a 4 bit register and uses data bits, D3–D0 to store the 4 bit address code (D7–D4 are ignored). The address code selects one of 16 UDC RAM locations for custom character generation. UDC RAM The UDC RAM is selected by setting FL=1, A4=0, A3=1. The RAM is comprised of a 7 x 5 bit RAM. As shown in Figure 11, address lines, A2–A0 select one of the 7 rows of the custom character. Data bits, D4–D0 determine the 5 bits of column data in each row. Each data bit corresponds to a LED. If the data bit is high, then the LED is on. If the data bit is low, the LED is off. To create a character, each of the 7 rows of column data need to be defined. See Figures 9 and 10 for logic. Flash RAM The Flash RAM allows the display to flash one or more of the characters being displayed. The Flash Ram is accessed by set- ting FL low. A4 and A3 are ignored. The Flash RAM is a 8 x 1 bit RAM with each bit corresponding to a digit address. Digit 0 is on the left side of the display and digit 7 is on the right side of the display. Address lines, A2–A0 select the digit address with A2 being the most significant digit and A0 being the least sig- nificant digit. Data bit, D0, sets and resets the flash bit for each digit. When D0 is high, the flash bit is set and when D0 is low, It is reset. See Figure 11. Figure 8. Character RAM Access Logic Figure 9. UDC Address Register and UDC Character RAM RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 1001111 Character Address for Digits 0–7 0 7 bit ASCII code for a Write Cycle 1010111 Character Address for Digits 0–7 0 7 bit ASCII code read during a Read Cycle 1001100 Character Address for Digits 0–7 1 D3–D0=UDC address for a Write Cycle 1010100 Character Address for Digits 0–7 1 D3–D0=UDC address for Read Data RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 1001100 Not used for UDC Address Register D3–D0=UDC RAM Address Code for Write Cycle UDC Address Register 1010100 Not used for UDC Address Register D3–D0=UDC RAM Address Code for Read Cycle 1001101 A2–A0=Character Row Address D4–D0=Character Column Data for Write Cycle UDC RAM 1010101 A2–A0=Character Row Address D4–D0=Character Column Data read during a Read Cycle |
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