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ADS5546IRGZT Datasheet(PDF) 8 Page - Texas Instruments |
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ADS5546IRGZT Datasheet(HTML) 8 Page - Texas Instruments |
8 / 50 page www.ti.com ADS5546 SLWS183C – NOVEMBER 2005 – REVISED OCTOBER 2006 TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued) For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this data sheet. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Duty cycle of differential clock, LVDS bit clock duty cycle (CLKOUTP-CLKOUTM) 45% 50% 55% 80 ≤ Fs ≤ 190 MSPS Rise time measured from –50 mV to 50 mV tr , Data rise time, Fall time measured from 50 mV to –50 mV 50 100 200 ps tf Data fall time 1 ≤ Fs ≤ 190 MSPS Rise time measured from –50 mV to 50 mV tCLKRISE, Output clock rise time, Fall time measured from 50 mV to –50 mV 50 100 200 ps tCLKFALL Output clock fall time 1 ≤ Fs ≤ 190 MSPS Output enable (OE) to valid data tOE Time to valid data after OE becomes active 1 µs delay PARALLEL CMOS MODE tsu Data setup time (5) Data valid(7) to 50% of CLKOUT rising edge 2.2 3 ns 50% of CLKOUT rising edge to data becoming th Data hold time (5) 0.5 0.9 ns invalid(7) Input clock rising edge zero-cross to 50% of tPDI Clock propagation delay 2.4 3.2 4 ns CLKOUT rising edge Duty cycle of output clock (CLKOUT) Output clock duty cycle 45% 80 ≤ Fs ≤ 190 MSPS Rise time measured from 20% to 80% of DRVDD tr, Data rise time, Fall time measured from 80% to 20% of 0.8 1.5 2 ns tf Data fall time DRVDD 1 ≤ Fs ≤ 190 MSPS Rise time measured from 20% to 80% of DRVDD tCLKRISE, Output clock rise time, Fall time measured from 80% to 20% of 0.4 0.8 1.2 ns tCLKFALL Output clock fall time DRVDD 1 ≤ Fs ≤ 190 MSPS Output enable (OE) to valid data tOE Time to valid data after OE becomes active 50 ns delay (7) Data valid refers to logic high of 2 V and logic low of 0.8 V 8 Submit Documentation Feedback |
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