Detailed Description

The MAX3822 is a 2.5Gbps quad limiting amplifier

designed for fiber applications with input sensitivities

as low as 20mVp-p. This device has internally terminat-

ed CML inputs with loss-of-power circuitry for each

channel, as well as a general loss-of-power indicator

valid for the whole part. Offset correction ensures low

pulse-width distortion (PWD) and reduced pattern-

dependent jitter (PDJ). A channel-select (CS) pin is

used to control the device’s mode of operation as sin-

gle, dual, or quad.

The inputs of the MAX3822 are typically connected to a

transimpedance amplifier (TIA) (MAX3825) found within

a fiber-optic link. The output signal from a TIA can con-

tain significant amounts of noise, and may vary in

amplitude over time. The MAX3822 limiting amplifier

quantizes the input signal, and outputs a voltage-limit-

ed waveform over a 40dB input dynamic range. Signal

input to this device passes through a buffer to a linear-

gain amplifier. This linear-gain amplifier (Figure 1) dri-

ves the power-detection circuitry and a chain of limiting

amplifiers leading to the CML output buffer.

The power-detection circuitry is used to indicate that

the data input voltage has fallen below the pro-

grammed threshold level. Each individual channel has

a power detector output (LOP1, LOP2, LOP3, LOP4).

The LOP output is low when any of the individual power-

detector outputs are low. A threshold adjustment pin

(VTH) programs the signal-detect threshold for all four

channels with a single external resistor. The offset-cor-

rection loop adjusts the input buffer bias until the CML

output buffer has a zero offset. This offset-correction

loop acts as a high-pass filter where signal components

below 150kHz are attenuated.

Input Buffer and Gain Stages

The MAX3822’s inputs are terminated with 50

(Figure 2). The inputs do not need to be AC-coupled if

the upstream TIA has CML outputs, but should be AC-

coupled if the differential logic levels are in any other

format. The differential input signal is passed through a

buffer, and then continues through two sets of differen-

tial amplifiers, each with an emitter-follower output

stage. The first differential amplifier provides approxi-

mately 10dB gain and a linear output for input signals

+3.3V, 2.5Gbps Quad Limiting Amplifier

6

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PIN

NAME

DESCRIPTION

26

OUT4+

Noninverted Data Output for Channel 4

28

OUT3-

Inverted Data Output for Channel 3

29

OUT3+

Noninverted Data Output for Channel 3

32

OUT2-

Inverted Data Output for Channel 2

33

OUT2+

Noninverted Data Output for Channel 2

35

OUT1-

Inverted Data Output for Channel 1

36

OUT1+

Noninverted Data Output for Channel 1

38

VTH

A resistor connected from this pin to ground sets the data input signal level at which the loss-of-

power outputs will be asserted.

41

CS

Channel-Select Input. To enable channel 1 only, leave CS open. To enable channels 1 and 2,

43

CZ2-

A capacitor connected between this pin and CZ2+ extends the time constant for the offset-

correction loop associated with channel 2. Maxim recommends a capacitor value of 0.033µF.

44

CZ2+

A capacitor connected between this pin and CZ2- extends the time constant for the offset-

correction loop associated with channel 2. Maxim recommends a capacitor value of 0.033µF.

46

CZ1-

A capacitor connected between this pin and CZ1+ extends the time constant for the offset-

correction loop associated with channel 1. Maxim recommends a capacitor value of 0.033µF.

47

CZ1+

A capacitor connected between this pin and CZ1- extends the time constant for the offset-

correction loop associated with channel 1. Maxim recommends a capacitor value of 0.033µF.

EP

Exposed

Pad

Ground. This must be soldered to a circuit board for proper thermal and electrical performance (see

Exposed Pad (EP) Package).

Pin Description (continued)