stage of the MAX3822, including package capacitance

and bond-wire inductance. The additional 0.4pF

capacitance on the output represents the ESD diode’s

junction capacitance and a small contribution by the

bond pad. For more information about the CML electri-

cal specifications and interfacing to other protocols,

refer to Application Note HFAN-1.0, Introduction to

LVDS, PECL, and CML.

Offset Correction

Each limiting amplifier on the MAX3822 provides

approximately 50dB of gain. An input offset as small as

1mV reduces the power-detection circuitry’s accuracy

and may cause deterministic jitter through an increase

of PWD.

Each of the MAX3822’s integrated limiting amplifiers

includes a DC cancellation loop that provides offset

correction to the CML output signal in addition to low-

frequency power-supply noise rejection. The DC can-

cellation loop consists of a low-pass filter and a

high-gain amplifier. The input voltage difference of the

CML output buffer is amplified, sent through a low-pass

filter, inverted, and summed up with the input signal

that drives the high-gain input stage. This removes from

the output signal all frequency components between

the cutoff frequency and DC. The low-frequency cutoff

of the DC cancellation loop is set by an external capac-

itor connected between CZ_+ and CZ_-.

Power Detection and Threshold Control

The MAX3822 incorporates a chatter-free loss-of-power

function that is used to determine if the input signal has

dropped below the programmed threshold level. The

power detector is implemented by comparing the DC-

rectified output of the first gain stage to the pro-

grammed loss-of-power threshold.

The threshold control circuitry enables programming of

LOP_ assert and deassert reference voltages by using

this voltage into a current. The current through this

resistor sets the power threshold level for the device

(see Typical Operating Characteristics, Loss-of-Power

+3.3V, 2.5Gbps Quad Limiting Amplifier

8

_______________________________________________________________________________________

50

Ω

50

Ω

ESD

DIODES

GND

IN+

IN-

0.4pF

0.4pF

1.5nH

1.5nH

0.2pF

0.2pF

DIE

PACKAGE

Figure 2. Input Structure

OUT-

OUT+

0.2pF

0.2pF

1.5nH

1.5nH

0.4pF

0.4pF

ESD

DIODES

50

Ω

GND

DIE

PACKAGE

50

Ω

Figure 3. Output Structure