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IDT71V25761 Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT71V25761 Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 23 page  OCTOBER 2000 DSC-5297/01 1 ©2000 Integrated Device Technology, Inc. Features x x x x x 128K x 36, 256K x 18 memory configurations x x x x x Supports high system speed: Commercial: – 200MHz 3.1ns clock access time Commercial and Industrial: – 183MHz 3.3ns clock access time – 166MHz 3.5ns clock access time x x x x x LBO input selects interleaved or linear burst mode x x x x x Self-timed write cycle with global write control ( GW),bytewrite enable ( BWE), and byte writes (BWx) x x x x x 3.3V core power supply x x x x x Power down controlled by ZZ input x x x x x 2.5V I/O x x x x x Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array Description The IDT71V25761/781 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V25761/781 SRAMs contain write, data, addressandcontrolregisters. InternallogicallowstheSRAMtogenerate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the systemdesigner,astheIDT71V25761/718canprovidefourcyclesofdata for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operationisselected( ADV=LOW),thesubsequentthreecyclesofoutput data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin. The IDT71V25761/781 SRAMs utilize IDT’s latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA). Pin Description Summary NOTE: 1. BW3 and BW4 are not applicable for the IDT71V25781. A0-A17 Address Inputs Input Synchronous CE Chip Enable Input Synchronous CS0, CS1 Chip Selects Input Synchronous OE Output Enable Input Asynchronous GW Global Write Enable Input Synchronous BWE Byte Write Enable Input Synchronous BW1, BW2, BW3, BW4(1) Individual Byte Write Selects Input Synchronous CLK Clock Input N/A ADV Burst Address Advance Input Synchronous ADSC Address Status (Cache Controller) Input Synchronous ADSP Address Status (Processor) Input Synchronous LBO Linear / Interleaved Burst Order Input DC ZZ Sleep Mode Input Asynchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply N/A VSS Ground Supply N/A 5297 tbl 01 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect IDT71V25761 IDT71V25781 |
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