Electronic Components Datasheet Search |
|
LC4512C-5F256C Datasheet(PDF) 28 Page - Lattice Semiconductor |
|
LC4512C-5F256C Datasheet(HTML) 28 Page - Lattice Semiconductor |
28 / 74 page Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet 28 ispMACH 4000V/B/C Internal Timing Parameters Over Recommended Operating Conditions Parameter Description -5 -75 -10 Units Min. Max. Min. Max. Min. Max. In/Out Delays tIN Input Buffer Delay — 0.95 — 1.50 — 2.00 ns tGOE Global OE Pin Delay — 4.04 — 6.04 — 7.04 ns tGCLK_IN Global Clock Input Buffer Delay — 1.83 — 2.28 — 3.28 ns tBUF Delay through Output Buffer — 1.00 — 1.50 — 1.50 ns tEN Output Enable Time — 0.96 — 0.96 — 0.96 ns tDIS Output Disable Time — 0.96 — 0.96 — 0.96 ns Routing/GLB Delays tROUTE Delay through GRP — 1.51 — 2.26 — 3.26 ns tMCELL Macrocell Delay — 1.05 — 1.45 — 1.95 ns tINREG Input Buffer to Macrocell Register Delay — 0.56 — 0.96 — 1.46 ns tFBK Internal Feedback Delay — 0.00 — 0.00 — 0.00 ns tPDb 5-PT Bypass Propagation Delay — 1.54 — 2.24 — 3.24 ns tPDi Macrocell Propagation Delay — 0.94 — 1.24 — 1.74 ns Register/Latch Delays tS D-Register Setup Time (Global Clock) 1.32 — 1.57 — 1.57 — ns tS_PT D-Register Setup Time (Product Term Clock) 1.32 — 1.32 — 1.32 — ns tST T-Register Setup Time (Global Clock) 1.52 — 1.77 — 1.77 — ns tST_PT T-Register Setup Time (Product Term Clock) 1.32 — 1.32 — 1.32 — ns tH D-Register Hold Time 1.68 — 2.93 — 3.93 — ns tHT T-Register Hold Time 1.68 — 2.93 — 3.93 — ns tSIR D-Input Register Setup Time (Global Clock) 1.52 — 1.57 — 1.57 — ns tSIR_PT D-Input Register Setup Time (Product Term Clock) 1.45 — 1.45 — 1.45 — ns tHIR D-Input Register Hold Time (Global Clock) 0.68 — 1.18 — 1.18 — ns tHIR_PT D-Input Register Hold Time (Product Term Clock) 0.68 — 1.18 — 1.18 — ns tCOi Register Clock to Output/Feedback MUX Time — 0.52 — 0.67 — 1.17 ns tCES Clock Enable Setup Time 2.25 — 2.25 — 2.25 — ns tCEH Clock Enable Hold Time 1.88 — 1.88 — 1.88 — ns tSL Latch Setup Time (Global Clock) 1.32 — 1.57 — 1.57 — ns tSL_PT Latch Setup Time (Product Term Clock) 1.32 — 1.32 — 1.32 — ns tHL Latch Hold Time 1.17 — 1.17 — 1.17 — ns tGOi Latch Gate to Output/Feedback MUX Time — 0.33 — 0.33 — 0.33 ns tPDLi Propagation Delay through Transparent Latch to Output/ Feedback MUX — 0.25 — 0.25 — 0.25 ns tSRi Asynchronous Reset or Set to Output/Feedback MUX Delay 0.28 — 0.28 — 0.28 — ns tSRR Asynchronous Reset or Set Recovery Time 1.67 — 1.67 — 1.67 — ns Control Delays tBCLK GLB PT Clock Delay — 1.12 — 1.12 — 0.62 ns tPTCLK Macrocell PT Clock Delay — 0.87 — 0.87 — 0.87 ns tBSR GLB PT Set/Reset Delay — 1.83 — 1.83 — 1.83 ns tPTSR Macrocell PT Set/Reset Delay — 2.51 — 3.41 — 3.41 ns |
Similar Part No. - LC4512C-5F256C |
|
Similar Description - LC4512C-5F256C |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |