Philips Semiconductors

Preliminary specification

87C54/87C58

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

3-223

Interrupt Priority Structure

The 87C54/87C58 has a 6-source two-level interrupt structure.

There are 3 SFRs associated with the interrupts. They are the IE

and IP which are identical in function to those on the 80C51.

The priority scheme for servicing the interrupts is the same as that

for the 80C51. An interrupt will be serviced as long as an interrupt of

equal or higher priority is not already being serviced. If an interrupt

of equal or higher level priority is being serviced, the new interrupt

will wait until it is finished before being serviced. If a lower priority

level interrupt is being serviced, it will be stopped and the new

interrupt serviced. When the new interrupt is finished, the lower

priority level interrupt that was stopped will be completed.

Table 3.

Interrupt Table

SOURCE

POLLING PRIORITY

REQUEST BITS

HARDWARE CLEAR?

VECTOR ADDRESS

X0

1

IE0

N (L) Y (T)

03H

T0

2

TP0

Y

0B

X1

3

IE1

N (L) Y (T)

13

T1

4

TF1

Y

1B

SP

5

R1, TI

N

23

T2

6

TF2, EXF2

N

2B

SCON Address = 98H

Reset Value = 0000 0000B

SM0/FE

SM1

SM2

REN

TB8

RB8

Tl

Rl

Bit Addressable

(SMOD0 = 0/1)*

Symbol

Function

FE

Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid

frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.

SM0

Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)

SM1

Serial Port Mode Bit 1

SM0

SM1

Mode

Description

Baud Rate**

0

0

0

shift register

0

1

1

8-bit UART

variable

1

0

2

9-bit UART

1

1

3

9-bit UART

variable

SM2

Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the

received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.

In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a

Given or Broadcast Address. In Mode 0, SM2 should be 0.

REN

Enables serial reception. Set by software to enable reception. Clear by software to disable reception.

TB8

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.

RB8

In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.

In Mode 0, RB8 is not used.

Tl

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the

other modes, in any serial transmission. Must be cleared by software.

Rl

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in

the other modes, in any serial reception (except see SM2). Must be cleared by software.

NOTE:

*SMOD0 is located at PCON6.

SU00043

Bit:

7654

321

0

Figure 1. SCON: Serial Port Control Register