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LC4256V-5T176C Datasheet(PDF) 30 Page - Lattice Semiconductor |
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LC4256V-5T176C Datasheet(HTML) 30 Page - Lattice Semiconductor |
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30 / 74 page  Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet 30 ispMACH 4032Z Internal Timing Parameters 1 Over Recommended Operating Conditions Parameter Description -35 -5 -75 Units Min. Max. Min. Max. Min. Max. In/Out Delays tIN Input Buffer Delay — 0.75 — 0.95 — 1.50 ns tGOE Global OE Pin Delay — 2.90 — 3.20 — 4.96 ns tGCLK_IN Global Clock Input Buffer Delay — 1.50 — 1.90 — 2.28 ns tBUF Delay through Output Buffer — 0.65 — 0.90 — 1.50 ns tEN Output Enable Time — 1.60 — 1.80 — 2.04 ns tDIS Output Disable Time — 1.35 — 1.60 — 2.96 ns Routing/GLB Delays tROUTE Delay through GRP — 1.70 — 2.25 — 2.26 ns tMCELL Macrocell Delay — 0.65 — 1.00 — 1.45 ns tINREG Input Buffer to Macrocell Register Delay — 0.91 — 0.75 — 0.65 ns tFBK Internal Feedback Delay — 0.35 — 0.50 — 0.70 ns tPDb 5-PT Bypass Propagation Delay — 0.40 — 0.90 — 2.24 ns tPDi Macrocell Propagation Delay — 0.25 — 0.35 — 1.24 ns Register/Latch Delays tS D-Register Setup Time (Global Clock) 0.60 — 0.70 — 1.57 — ns tS_PT D-Register Setup Time (Product Term Clock) 1.55 — 1.50 — 1.65 — ns tST T-Register Setup Time (Global Clock) 0.90 — 0.90 — 1.77 — ns tST_PT T-register Setup Time (Product Term Clock) 1.75 — 1.50 — 1.32 — ns tH D-Register Hold Time 1.60 — 2.30 — 2.93 — ns tHT T-Resister Hold Time 1.60 — 2.30 — 2.93 — ns tSIR D-Input Register Setup Time (Global Clock) 0.84 — 1.40 — 1.83 — ns tSIR_PT D-Input Register Setup Time (Product Term Clock) 1.45 — 1.45 — 1.45 — ns tHIR D-Input Register Hold Time (Global Clock) 1.16 — 0.80 — 0.87 — ns tHIR_PT D-Input Register Hold Time (Product Term Clock) 0.88 — 1.00 — 1.18 — ns tCOi Register Clock to Output/Feedback MUX Time — 0.45 — 0.55 — 0.67 ns tCES Clock Enable Setup Time 1.00 — 1.40 — 2.00 — ns tCEH Clock Enable Hold Time 0.00 — 0.00 — 0.00 — ns tSL Latch Setup Time (Global Clock) 0.65 — 1.02 — 1.57 — ns tSL_PT Latch Setup Time (Product Term Clock) 1.75 — 1.32 — 1.32 — ns tHL Latch Hold Time 1.40 — 1.17 — 1.17 — ns tGOi Latch Gate to Output/Feedback MUX Time — 0.40 — 0.33 — 0.33 ns tPDLi Propagation Delay through Transparent Latch to Output/Feed- back MUX — 0.30 — 0.25 — 0.25 ns tSRi Asynchronous Reset or Set to Output/Feedback MUX Delay — 1.00 — 0.28 — 0.28 ns tSRR Asynchronous Reset or Set Recovery Delay — 2.00 — 1.67 — 1.67 ns Control Delays tBCLK GLB PT Clock Delay — 1.50 — 1.12 — 1.12 ns tPTCLK Macrocell PT Clock Delay — 1.70 — 0.87 — 0.87 ns tBSR GLB PT Set/Reset Delay — 1.10 — 1.83 — 1.83 ns tPTSR Macrocell PT Set/Reset Delay — 0.50 — 1.87 — 3.41 ns tGPTOE Global PT OE Delay — 2.45 — 3.00 — 3.20 ns |
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Similar Description - LC4256V-5T176C |
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