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Z8038220ASC Datasheet(PDF) 10 Page - Zilog, Inc. |
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Z8038220ASC Datasheet(HTML) 10 Page - Zilog, Inc. |
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10 / 77 page  Z80382/Z8L382 High-Performance Data Communications Processors Zilog 10 P R E L I M I N A R Y DS97Z382000 AC CHARACTERISTICS 380C Processor Timing (See Figure 4) Specifications apply over Standard Operating Conditions unless otherwise noted. C L = 50 pF for outputs. Symbol Parameter Z80382 Z8L382 Notes Unit Min. Max. Min. Max. t1 Clock Cycle Time 25 DC 50 DC 1 ns t2 Clock High Time 10 20 1 ns t3 Clock Low Time 10 20 1 ns t4 Clock Rise Time 3 5 1 ns t5 Clock Fall Time 3 5 1 ns t6 CLKI Low to BUSCLK High Delay 25 35 ns t7 CLKI High to BUSCLK Low Delay 25 35 ns t8 BUSCLK High to Output Valid 10 10 2 ns t9 BUSCLK Low to Output Valid 10 10 3 ns t10 Input Setup to BUSCLK Rise 10 15 4 ns t11 Input Hold from BUSCLK High 0 0 4 ns t12 /BUSREQ Setup to BUSCLK Fall 10 15 5 ns t13 /BUSREQ Hold from BUSCLK Low 0 0 5 ns t14 /WAIT Setup to BUSCLK Rise 10 15 6 ns t15 /WAIT Hold from BUSCLK High 0 0 6 ns t16 /WAIT Setup to BUSCLK Fall 15 15 6 ns t17 /WAIT Hold from BUSCLK Low 0 0 6 ns t18 /NMI Width Low 15 15 ns t19 /RESET Width Low 10 10 t1 t20 /INT1, /INT2, /INT3 Low Width 15 15 7 ns t21 /INT1, /INT2, /INT3 High Width 15 15 7 ns Notes: 1. Applies to the oscillator or external clock input. The maximum internal clock frequency (BUSCLK) is limited to 20 MHz for the Z80382 and 10 MHz for the Z8L382. Input clock frequencies greater than these values must use the CLKI/2 mode for creating BUSCLK. This is the default state after Reset. 2. Applies to A23-0, /BHEN, /BLEN, IOCLK, /IOCS1, /IOCS2, /ROMCS, /RAMCSL, /RAMCSH, /M1, /BUSACK, /MRD, /MWR, /TRE- FA, /TREFC, /TREFR 3. Applies to D15-0, /HALT, /STNBY, /IORQ, /IORD, /IOWR, /MSIZE, /BUSACK, /MRD, /MWR, /TREFC, /TREFR 4. Applicable for Data Bus and /MSIZE inputs. 5. /BUSREQ can also be asserted/deasserted asynchronously. 6. External waits asserted at /WAIT input. 7. In edge-triggered mode. |
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