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SN74GTLP21395DWR Datasheet(PDF) 1 Page - Texas Instruments |
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SN74GTLP21395DWR Datasheet(HTML) 1 Page - Texas Instruments |
1 / 21 page SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES350C – JUNE 2001 – REVISED NOVEMBER 2001 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes D OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference D Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels D Split LVTTL Port Provides a Feedback Path for Control and Diagnostics Monitoring D Y Outputs Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required D LVTTL Interfaces Are 5-V Tolerant D High-Drive GTLP Outputs (100 mA) D LVTTL Outputs (–12 mA/12 mA) D Variable Edge-Rate Control (ERC) Input Selects GTLP Rise and Fall Times for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads D Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion D Polarity Control Selects True or Complementary Outputs D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) description The SN74GTLP21395 is two 1-bit, high-drive, 3-wire bus transceivers that provide LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation for applications, such as primary and secondary clocks, that require individual output-enable and true/complement controls. The device allows for transparent and inverted transparent modes of data transfer with separate LVTTL input and LVTTL output pins, which provide a feedback path for control and diagnostics monitoring. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels and is designed especially to work with the Texas Instruments 3.3-V 1394 backplane physical-layer controller. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC circuitry, and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuitry minimizes bus settling time, and have been designed and tested using several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes, with equivalent load impedance down to 11 Ω. The Y outputs, which are designed to sink up to 12 mA, include equivalent 26- Ω resistors to reduce overshoot and undershoot. Copyright 2001, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DGV, DW, OR PW PACKAGE (TOP VIEW) 1Y 1T/C 2Y GND 1OEAB VCC 1A GND 2A 2OEAB 1OEBY 2T/C 2OEBY GND 1B ERC 2B GND VREF BIAS VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 OEC and TI-OPC are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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