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A625308R-70L Datasheet(PDF) 2 Page - AMIC Technology |
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A625308R-70L Datasheet(HTML) 2 Page - AMIC Technology |
2 / 13 page A625308 Series Preliminary 32K X 8 BIT CMOS SRAM PRELIMINARY (December, 2000, Version 0.2) 1 AMIC Technology, Inc. Features n External Operating Voltage: 4.5V to 5.5V n Access times: 70 ns (max.) n Current: A625308-L series: Operating: 70mA (max.) Standby: 100 µA(max.) A625308-S series: Operating: 70mA (max.) Standby: 25 µA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL compatible n Common I/O using three-state output n Data retention voltage: 2.0V (min.) n Available in 28-pin SOP and TSOP (forward and reverse type) packages General Description The A625308 is a low operating current 262,144-bit static random access memory organized as 32,768 words by 8 bits and operates on a single 5V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Minimum standby power is drawn by this device when CE is at a high level, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 2.0V. Pin Configurations n SOP n TSOP A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE OE A11 A9 A8 A13 WE VCC A10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 A625308V 1 9 28 20 A11 2 3 4 5 6 7 8 10 11 12 13 14 A9 A8 A13 A14 A12 A7 A6 A5 A4 A3 27 26 25 24 23 22 21 19 18 17 16 15 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A10 VCC I/O7 OE WE CE A625308R 1 9 28 20 A4 2 3 4 5 6 7 8 10 11 12 13 14 A5 A6 A7 VCC A13 A8 A9 A11 27 26 25 24 23 22 21 19 18 17 16 15 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 A10 A2 A14 A0 A3 A12 A1 WE OE CE |
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