Single LNB Supply and Control Voltage Regulator

A8290

11

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

The IRQ output becomes active when either the A8290 first

recognizes a fault condition, or at power-on, when the main sup-

master addresses the A8290 with the Read/Write bit set (caus-

ing a read). Fault conditions are indicated by the TSD, VUV, and

OCP bits and are latched in the Status register. See the Status reg-

ister section for full description.

The DIS, PNG, CAD and TDET status bits do not cause an in-

terrupt. All these bits are continually updated, apart from the DIS

bit, which changes when the LNB is either disabled, intentionally

or due to a fault, or is enabled.

When the master recognizes an interrupt, it addresses all

slaves connected to the interrupt line in sequence, and then reads

the status register to determine which device is requesting atten-

tion. The A8290 latches all conditions in the Status register until

the completion of the data read. The action at the resampling

point is further defined in the Status Register section. The bits in

the Status register are defined such that the all-zero condition in-

dicates that the A8290 is fully active with no fault conditions.

does not respond to any requests until the internal logic supply

point, the IRQ output goes active, and the VUV bit is set. After

the A8290 acknowledges the address, the IRQ flag is reset. After

the master reads the status registers, the registers are updated with

the VUV reset.

0

0

0

1

0

A1

A0

1

AK

D6

D5

D4

D3

D2

D1

D0

D7

NAK

Status Register 1

Address

Start

R

Stop

1

2

3

4

5

6

7

8

9

SDA

SCL

IRQ

Fault

Event

Reload

Status Register

Read after Interrupt