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LC4256V-5F256BI Datasheet(PDF) 29 Page - Lattice Semiconductor |
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LC4256V-5F256BI Datasheet(HTML) 29 Page - Lattice Semiconductor |
29 / 74 page Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet 29 tGPTOE Global PT OE Delay — 5.58 — 5.58 — 5.78 ns tPTOE Macrocell PT OE Delay — 3.58 — 4.28 — 4.28 ns Timing v.3.1 Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details. ispMACH 4000V/B/C Internal Timing Parameters (Cont.) Over Recommended Operating Conditions Parameter Description -5 -75 -10 Units Min. Max. Min. Max. Min. Max. |
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